KMAC/UNMASKED Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.135m	16.410ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.230s	47.145us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	107.632us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.990s	5.159ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	12.640s	2.401ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	5.090s	205.483us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	107.632us	20	20	100.00
		kmac_csr_aliasing	12.640s	2.401ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	19.939us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	39.570us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	46.856m	132.910ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.487m	51.337ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.479m	1.674s	50	50	100.00
		kmac_test_vectors_sha3_256	33.563m	374.964ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.208m	286.336ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.435m	250.522ms	50	50	100.00
		kmac_test_vectors_shake_128	1.534h	1.034s	50	50	100.00
		kmac_test_vectors_shake_256	1.348h	1.540s	50	50	100.00
		kmac_test_vectors_kmac	5.600s	717.138us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.650s	1.138ms	50	50	100.00
V2	sideload	kmac_sideload	7.898m	86.528ms	50	50	100.00
V2	app	kmac_app	5.917m	135.397ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.732m	70.317ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.011m	123.309ms	50	50	100.00
V2	error	kmac_error	6.641m	36.856ms	50	50	100.00
V2	key_error	kmac_key_error	7.720s	7.052ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.000s	2.038ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.470s	7.984ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.477m	55.362ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	29.010s	2.546ms	50	50	100.00
V2	stress_all	kmac_stress_all	32.028m	170.677ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	17.283us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	47.401us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.510s	149.158us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.510s	149.158us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.230s	47.145us	5	5	100.00
		kmac_csr_rw	1.190s	107.632us	20	20	100.00
		kmac_csr_aliasing	12.640s	2.401ms	5	5	100.00
		kmac_same_csr_outstanding	2.970s	1.447ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.230s	47.145us	5	5	100.00
		kmac_csr_rw	1.190s	107.632us	20	20	100.00
		kmac_csr_aliasing	12.640s	2.401ms	5	5	100.00
		kmac_same_csr_outstanding	2.970s	1.447ms	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.510s	59.723us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.510s	59.723us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.510s	59.723us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.510s	59.723us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.290s	454.152us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.073m	17.240ms	5	5	100.00
		kmac_tl_intg_err	5.760s	260.633us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.760s	260.633us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	29.010s	2.546ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.135m	16.410ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.898m	86.528ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.510s	59.723us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.073m	17.240ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.073m	17.240ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.073m	17.240ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.135m	16.410ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	29.010s	2.546ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.073m	17.240ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.095m	11.882ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.135m	16.410ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.137m	97.885ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			1252	1290	97.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.60	96.58	92.45	100.00	89.77	94.67	98.84	96.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:756) [kmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 26 failures:
- Test kmac_stress_all_with_rand_reset has 26 failures.
  - 0.kmac_stress_all_with_rand_reset.74914774207352750243811152090899324919381128971509823973423281707345127647158
    Line 1156, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65473599925 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 65473599925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.56727741455348571982643699202235810764389372524957180389859072925137446679459
    Line 717, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 58620281403 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 58620281403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 15.kmac_stress_all_with_rand_reset.22461519201284076071533791184232863409398763789863160922824401822870987747567
    Line 887, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36228474840 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 36228474840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.kmac_stress_all_with_rand_reset.55737116743021046194144891013536319016565522061125782484849429292030865872496
    Line 490, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40298437875 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 40298437875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app has 3 failures.

8.kmac_app.6414194607536560036610901733308301754726918649584694892583417501587045983118
Line 389, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_app/latest/run.log

  UVM_FATAL @ 3022218374 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (182 [0xb6] vs 70 [0x46]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3022218374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.kmac_app.78399783395740916338181849929579676179910796970303385975662361906979745109336
Line 877, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_app/latest/run.log

  UVM_FATAL @ 11035528237 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (9 [0x9] vs 101 [0x65]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11035528237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 23.kmac_stress_all_with_rand_reset.50126267013286568211788304599256540540001998985927871378360219609013966767812
    Line 1703, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 37375637854 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (49 [0x31] vs 109 [0x6d]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 37375637854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 48.kmac_key_error.56060090702203190365746739270058596100577722451659389663086968695695662551328
    Line 261, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1786038773 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1786038773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```