KMAC/UNMASKED Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.273m	26.828ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.060s	62.698us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	128.583us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.690s	4.987ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.060s	2.175ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.500s	101.823us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	128.583us	20	20	100.00
		kmac_csr_aliasing	10.060s	2.175ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	27.691us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.420s	36.018us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.864m	258.557ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.494m	23.609ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.047m	1.978s	50	50	100.00
		kmac_test_vectors_sha3_256	35.903m	877.949ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.381m	282.483ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.020m	205.554ms	50	50	100.00
		kmac_test_vectors_shake_128	1.788h	4.273s	50	50	100.00
		kmac_test_vectors_shake_256	1.555h	4.355s	50	50	100.00
		kmac_test_vectors_kmac	5.690s	3.551ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.460s	275.545us	50	50	100.00
V2	sideload	kmac_sideload	6.929m	20.636ms	50	50	100.00
V2	app	kmac_app	5.804m	17.971ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.472m	16.416ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.527m	60.473ms	50	50	100.00
V2	error	kmac_error	6.787m	57.392ms	48	50	96.00
V2	key_error	kmac_key_error	7.130s	5.014ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.260s	29.405ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.540s	1.943ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.047m	13.420ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	59.740s	1.018ms	50	50	100.00
V2	stress_all	kmac_stress_all	31.152m	68.051ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	34.103us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	38.792us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.270s	1.544ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.270s	1.544ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.060s	62.698us	5	5	100.00
		kmac_csr_rw	1.210s	128.583us	20	20	100.00
		kmac_csr_aliasing	10.060s	2.175ms	5	5	100.00
		kmac_same_csr_outstanding	2.590s	289.623us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.060s	62.698us	5	5	100.00
		kmac_csr_rw	1.210s	128.583us	20	20	100.00
		kmac_csr_aliasing	10.060s	2.175ms	5	5	100.00
		kmac_same_csr_outstanding	2.590s	289.623us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	202.432us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	202.432us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	202.432us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	202.432us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.310s	281.774us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.398m	48.932ms	5	5	100.00
		kmac_tl_intg_err	5.220s	486.733us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.220s	486.733us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	59.740s	1.018ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.273m	26.828ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.929m	20.636ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	202.432us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.398m	48.932ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.398m	48.932ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.398m	48.932ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.273m	26.828ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	59.740s	1.018ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.398m	48.932ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.243m	17.887ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.273m	26.828ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	38.389m	673.682ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			1243	1290	96.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.45	96.18	92.38	100.00	89.77	94.52	98.84	96.45

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:815) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test kmac_stress_all_with_rand_reset has 33 failures.
  - 0.kmac_stress_all_with_rand_reset.42399991345961345556190484012349339410839557378618685015491579271990338624048
    Line 1140, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51686428265 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 51686428265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.90746008563532499258024502624926596165560495146667149864609646309722392779151
    Line 479, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7685034810 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7685034810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 2.kmac_stress_all_with_rand_reset.35325762145307052715735299124784995961382402786020691180690692676893767857746
    Line 1066, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34407453994 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 34407453994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.kmac_stress_all_with_rand_reset.37476082642181096288207498572461651842699658376496126625509901796514773910088
    Line 768, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9563858330 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9563858330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

Test kmac_error has 2 failures.

0.kmac_error.92788507887123809234652449900376652030115550540741310055063652059281641310478
Line 783, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.kmac_error.86478081939291046310161895740034161137491901713641862327249253119551250048452
Line 1086, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_burst_write has 2 failures.

5.kmac_burst_write.28086296129542852070656149264915903573456779443526321544944168572769768586115
Line 1190, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_burst_write.43191520588619214059064636728079253157346898381746300692906337578125190256391
Line 645, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_mubi has 1 failures.

5.kmac_mubi.4866156536814106642614766935277527276885310256495395882290411326914080891256
Line 555, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_mubi/latest/run.log

  UVM_FATAL @ 2024103277 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (67 [0x43] vs 199 [0xc7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2024103277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

14.kmac_app.83384973602046176302064148761955450741161789433925145143175176831813306259986
Line 477, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_app/latest/run.log

  UVM_FATAL @ 1591170272 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (77 [0x4d] vs 44 [0x2c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1591170272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

46.kmac_stress_all.31667456666495057325694498331288486189438183442048802247258507882421574815618
Line 2325, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest/run.log

  UVM_FATAL @ 34160763467 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (229 [0xe5] vs 158 [0x9e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 34160763467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---