KMAC/UNMASKED Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.178m	12.922ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.250s	534.179us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.170s	33.507us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.630s	4.035ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.340s	1.578ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.700s	279.983us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.170s	33.507us	20	20	100.00
		kmac_csr_aliasing	9.340s	1.578ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	17.458us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.270s	108.135us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.265m	747.193ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.078m	17.652ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.984m	408.524ms	50	50	100.00
		kmac_test_vectors_sha3_256	36.038m	1.150s	50	50	100.00
		kmac_test_vectors_sha3_384	30.225m	1.365s	50	50	100.00
		kmac_test_vectors_sha3_512	19.759m	612.463ms	50	50	100.00
		kmac_test_vectors_shake_128	1.585h	2.149s	50	50	100.00
		kmac_test_vectors_shake_256	1.296h	1.676s	50	50	100.00
		kmac_test_vectors_kmac	5.620s	1.674ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.000s	994.166us	50	50	100.00
V2	sideload	kmac_sideload	8.331m	87.605ms	50	50	100.00
V2	app	kmac_app	5.364m	24.822ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.804m	79.959ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.301m	23.577ms	49	50	98.00
V2	error	kmac_error	7.273m	24.147ms	50	50	100.00
V2	key_error	kmac_key_error	10.170s	16.525ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.130s	4.801ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.310s	2.838ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.106m	23.571ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	52.320s	1.105ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.529m	89.764ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	133.562us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	23.363us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.770s	418.008us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.770s	418.008us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.250s	534.179us	5	5	100.00
		kmac_csr_rw	1.170s	33.507us	20	20	100.00
		kmac_csr_aliasing	9.340s	1.578ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	495.172us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.250s	534.179us	5	5	100.00
		kmac_csr_rw	1.170s	33.507us	20	20	100.00
		kmac_csr_aliasing	9.340s	1.578ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	495.172us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	66.922us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	66.922us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	66.922us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	66.922us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.270s	1.557ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.218m	21.039ms	5	5	100.00
		kmac_tl_intg_err	5.120s	496.772us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.120s	496.772us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	52.320s	1.105ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.178m	12.922ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.331m	87.605ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	66.922us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.218m	21.039ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.218m	21.039ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.218m	21.039ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.178m	12.922ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	52.320s	1.105ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.218m	21.039ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.176m	65.695ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.178m	12.922ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.282m	306.828ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			1243	1290	96.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.31	96.18	92.38	100.00	88.64	94.52	98.84	96.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:

  • Test kmac_stress_all_with_rand_reset has 37 failures.

    • 0.kmac_stress_all_with_rand_reset.8994762634832083056489137338365773624887813369352816424140506541746622449364
      Line 286, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1183089579 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1183089579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.32262415509284201558002261074860791449628736006037598335266191568786173432533
      Line 1232, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30894476990 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 30894476990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 35 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:

  • Test kmac_stress_all_with_rand_reset has 6 failures.

    • 4.kmac_stress_all_with_rand_reset.105566722189097452700324038962306279691466880599880092599016678633624045169375
      Line 284, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 376851540 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 376851540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.kmac_stress_all_with_rand_reset.80493023215949773270774754422708584071217986629975955290062312607605147775653
      Line 868, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17980313648 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 17980313648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test kmac_burst_write has 2 failures.

    • 18.kmac_burst_write.97429102067758005371348666816823600391077113494296245514996667768801948173799
      Line 765, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.kmac_burst_write.112670830524089879439195439454427223396300107782620292978450222063862007268310
      Line 1130, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 4.kmac_entropy_refresh.22581308018166017804013928245103583053605567492353456689818285905514892848721
      Line 551, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 10405101284 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (164 [0xa4] vs 154 [0x9a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 10405101284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.cfg_regwen has 1 failures:

  • Test kmac_app has 1 failures.

    • 19.kmac_app.103901247410755756369497881813208993825851698342818148022019845306792594891859
      Line 692, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_app/latest/run.log

        UVM_ERROR @ 8182329000 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: kmac_reg_block.cfg_regwen
        UVM_INFO @ 8182329000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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