KMAC/UNMASKED Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.201m	14.543ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	112.324us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	40.526us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.320s	996.446us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.650s	1.053ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	162.178us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	40.526us	20	20	100.00
		kmac_csr_aliasing	10.650s	1.053ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	40.581us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	40.129us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.169m	128.485ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.714m	34.517ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.953m	927.287ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.395m	96.266ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.083m	298.373ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.726m	49.728ms	50	50	100.00
		kmac_test_vectors_shake_128	1.526h	1.554s	50	50	100.00
		kmac_test_vectors_shake_256	1.378h	902.616ms	50	50	100.00
		kmac_test_vectors_kmac	5.470s	2.956ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.900s	1.563ms	50	50	100.00
V2	sideload	kmac_sideload	7.022m	15.914ms	50	50	100.00
V2	app	kmac_app	5.826m	70.681ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.594m	47.677ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.328m	71.107ms	49	50	98.00
V2	error	kmac_error	7.262m	40.334ms	50	50	100.00
V2	key_error	kmac_key_error	11.340s	20.063ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.910s	4.119ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.080s	2.043ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.212m	73.327ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	35.540s	3.291ms	50	50	100.00
V2	stress_all	kmac_stress_all	34.721m	27.766ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.840s	50.296us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	108.378us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.350s	401.230us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.350s	401.230us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	112.324us	5	5	100.00
		kmac_csr_rw	1.180s	40.526us	20	20	100.00
		kmac_csr_aliasing	10.650s	1.053ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	1.742ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	112.324us	5	5	100.00
		kmac_csr_rw	1.180s	40.526us	20	20	100.00
		kmac_csr_aliasing	10.650s	1.053ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	1.742ms	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.520s	90.251us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.520s	90.251us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.520s	90.251us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.520s	90.251us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.890s	189.326us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.194m	74.081ms	5	5	100.00
		kmac_tl_intg_err	5.250s	253.758us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.250s	253.758us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	35.540s	3.291ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.201m	14.543ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.022m	15.914ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.520s	90.251us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.194m	74.081ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.194m	74.081ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.194m	74.081ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.201m	14.543ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	35.540s	3.291ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.194m	74.081ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.810m	48.346ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.201m	14.543ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	44.272m	595.214ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			1242	1290	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.45	96.18	92.38	100.00	89.77	94.52	98.84	96.45

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test kmac_stress_all_with_rand_reset has 37 failures.
  - 0.kmac_stress_all_with_rand_reset.64194455263243869568054915810026331105419817747820200308352791520287927209726
    Line 795, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 72123572128 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 72123572128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.57526274122341512804057031723016941150845306558941974559897773145513103353663
    Line 526, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 68815180103 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 68815180103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 1 failures.

0.kmac_app.87398144329485092707435566724513123133039533349383585827568986013412419352804
Line 491, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app/latest/run.log

  UVM_FATAL @ 50608828156 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (22 [0x16] vs 30 [0x1e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 50608828156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

8.kmac_mubi.92658224965788664445386367384778049411282332106414059654053260011038532210220
Line 367, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_mubi/latest/run.log

  UVM_FATAL @ 2572837701 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (62 [0x3e] vs 194 [0xc2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2572837701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

11.kmac_stress_all.15944492803037077515177765733933940889491621654585644779678729646019559749492
Line 1629, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest/run.log

  UVM_FATAL @ 49393801464 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (35 [0x23] vs 240 [0xf0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 49393801464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

29.kmac_entropy_refresh.4097678224280192846148939553574714058976341643529526958592358931187855205541
Line 329, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6518626708 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (190 [0xbe] vs 110 [0x6e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6518626708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 3.kmac_stress_all_with_rand_reset.73865212926458933684155463406752347474061394294413036302159253461560465852806
    Line 533, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25357348534 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 25357348534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.34394816666429897924836663683226119129860716016443036252149521574701824646711
    Line 627, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 651851574 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 651851574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 38.kmac_burst_write.56124090107597341472270401474192047679446547963707810953132216296340908049061
    Line 668, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.kmac_burst_write.79796193881961843849797954429335428848276385804653314311338818437392104601395
    Line 554, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 26.kmac_key_error.112694545648888411103305125702601890455872085038535034853380825822584379594530
    Line 261, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1955296067 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1955296067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```