KMAC/UNMASKED Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.128m	18.942ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	30.856us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.160s	30.244us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.360s	299.481us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.510s	511.016us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.590s	97.173us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.160s	30.244us	20	20	100.00
		kmac_csr_aliasing	9.510s	511.016us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	69.553us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.400s	73.578us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	42.732m	325.342ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.224m	27.431ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.581m	404.316ms	50	50	100.00
		kmac_test_vectors_sha3_256	30.565m	259.099ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.910m	73.079ms	50	50	100.00
		kmac_test_vectors_sha3_512	16.941m	195.025ms	50	50	100.00
		kmac_test_vectors_shake_128	1.645h	1.998s	49	50	98.00
		kmac_test_vectors_shake_256	1.279h	225.562ms	50	50	100.00
		kmac_test_vectors_kmac	5.620s	1.092ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.940s	1.877ms	50	50	100.00
V2	sideload	kmac_sideload	7.492m	152.592ms	49	50	98.00
V2	app	kmac_app	5.675m	49.923ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.093m	45.272ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.554m	89.187ms	48	50	96.00
V2	error	kmac_error	8.068m	161.455ms	49	50	98.00
V2	key_error	kmac_key_error	7.450s	16.711ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.150s	2.621ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.910s	10.621ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.093m	59.564ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.830s	1.941ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.228m	522.742ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.820s	27.902us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	36.325us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.910s	86.484us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.910s	86.484us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	30.856us	5	5	100.00
		kmac_csr_rw	1.160s	30.244us	20	20	100.00
		kmac_csr_aliasing	9.510s	511.016us	5	5	100.00
		kmac_same_csr_outstanding	2.630s	120.546us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	30.856us	5	5	100.00
		kmac_csr_rw	1.160s	30.244us	20	20	100.00
		kmac_csr_aliasing	9.510s	511.016us	5	5	100.00
		kmac_same_csr_outstanding	2.630s	120.546us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.610s	80.510us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.610s	80.510us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.610s	80.510us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.610s	80.510us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.960s	551.059us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	57.150s	3.632ms	5	5	100.00
		kmac_tl_intg_err	5.700s	2.253ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.700s	2.253ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.830s	1.941ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.128m	18.942ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.492m	152.592ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.610s	80.510us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	57.150s	3.632ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	57.150s	3.632ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	57.150s	3.632ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.128m	18.942ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.830s	1.941ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	57.150s	3.632ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.515m	43.185ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.128m	18.942ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	50.695m	692.889ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			1239	1290	96.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.60	96.18	92.17	100.00	90.91	94.52	98.84	96.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:
- Test kmac_stress_all_with_rand_reset has 39 failures.
  - 0.kmac_stress_all_with_rand_reset.1121818968476655272227215341835948690311061548318174366912986477087090778929
    Line 326, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1086297026 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1086297026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.110185430608389227911135393877590771540051474293236394964735188136468283193979
    Line 268, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3871192312 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3871192312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 37 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 7.kmac_stress_all_with_rand_reset.1027078810619520398276402256781305796806366970933588579109581643071055741027
    Line 613, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10440721539 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 10440721539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.kmac_stress_all_with_rand_reset.105764758166161932985494826395586585093291943070098374829479297753175530055827
    Line 1032, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21177169693 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 21177169693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 2.kmac_test_vectors_shake_128.105025235451611581285580870194601137256039238375185121814382684847124401592934
    Line 5627, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 5.kmac_entropy_refresh.1582120333887363436494111392567411821657975535694283281576703587200923345301
    Line 854, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 13.kmac_error.98586233056565990425792001276907962134604400951552516913072876664531904533767
    Line 912, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_sideload has 1 failures.
  - 36.kmac_sideload.221185908165694619403942073102027263624881389528617427722644554618168280399
    Line 1028, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 8.kmac_key_error.23768917012904338599502954574434259274934263816834743857995537161964916267197
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 180662354 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 180662354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 19.kmac_entropy_refresh.105766114220615071925731512334152285214807847083279963730973823562252937294118
    Line 361, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 16792398762 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (86 [0x56] vs 104 [0x68]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16792398762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/UNMASKED Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `919341eb22`