KMAC/UNMASKED Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.106m	8.444ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.040s	61.647us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	26.427us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.080s	7.787ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.730s	1.423ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	250.068us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	26.427us	20	20	100.00
		kmac_csr_aliasing	9.730s	1.423ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	29.356us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.360s	39.012us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.086m	125.195ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.726m	33.156ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.841m	1.357s	50	50	100.00
		kmac_test_vectors_sha3_256	33.645m	381.369ms	50	50	100.00
		kmac_test_vectors_sha3_384	28.445m	770.571ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.680m	298.229ms	50	50	100.00
		kmac_test_vectors_shake_128	1.522h	1.289s	50	50	100.00
		kmac_test_vectors_shake_256	1.336h	1.963s	50	50	100.00
		kmac_test_vectors_kmac	5.680s	1.381ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.610s	478.411us	50	50	100.00
V2	sideload	kmac_sideload	7.464m	85.476ms	50	50	100.00
V2	app	kmac_app	6.154m	13.316ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.149m	27.337ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.444m	89.385ms	49	50	98.00
V2	error	kmac_error	7.312m	20.664ms	50	50	100.00
V2	key_error	kmac_key_error	6.800s	5.006ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.150s	2.174ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.960s	1.469ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.180m	31.037ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.090s	1.441ms	50	50	100.00
V2	stress_all	kmac_stress_all	38.237m	33.469ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.900s	19.529us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	17.791us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.330s	133.716us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.330s	133.716us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.040s	61.647us	5	5	100.00
		kmac_csr_rw	1.200s	26.427us	20	20	100.00
		kmac_csr_aliasing	9.730s	1.423ms	5	5	100.00
		kmac_same_csr_outstanding	2.680s	132.855us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.040s	61.647us	5	5	100.00
		kmac_csr_rw	1.200s	26.427us	20	20	100.00
		kmac_csr_aliasing	9.730s	1.423ms	5	5	100.00
		kmac_same_csr_outstanding	2.680s	132.855us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.670s	68.760us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.670s	68.760us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.670s	68.760us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.670s	68.760us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.110s	202.031us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.264m	23.015ms	5	5	100.00
		kmac_tl_intg_err	5.460s	4.004ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.460s	4.004ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.090s	1.441ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.106m	8.444ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.464m	85.476ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.670s	68.760us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.264m	23.015ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.264m	23.015ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.264m	23.015ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.106m	8.444ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.090s	1.441ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.264m	23.015ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.755m	191.496ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.106m	8.444ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.021m	297.525ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			1247	1290	96.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.41	96.18	92.13	100.00	89.77	94.52	98.84	96.45

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test kmac_stress_all_with_rand_reset has 28 failures.
  - 1.kmac_stress_all_with_rand_reset.60991380681560708280893250049568691046975128539315982301357357970869467685922
    Line 868, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17250269372 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17250269372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.74521912397975208918935199821133446457997336742258505097974222658851044463861
    Line 481, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 260909887120 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 260909887120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.28411933276480388995451443257114467285549800010356918984462444681646340137492
    Line 554, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 119651419262 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 119651419262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_stress_all_with_rand_reset.32441691401578534406150956214073682548927494949030223381519559557576947405166
    Line 260, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @   7479713 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @   7479713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all_with_rand_reset has 2 failures.

3.kmac_stress_all_with_rand_reset.114591822479230059399458520754149159875680994274660331951692256953489389070877
Line 483, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 2736746051 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (81 [0x51] vs 227 [0xe3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2736746051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.kmac_stress_all_with_rand_reset.102773832703092364047498593279560411702279718352336222781647344963320178008359
Line 1715, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 105432696558 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (63 [0x3f] vs 214 [0xd6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 105432696558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

30.kmac_entropy_refresh.52986746572394456844810028221615052955132977282332666292725476935620289990177
Line 335, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3960265502 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (75 [0x4b] vs 95 [0x5f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3960265502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

32.kmac_app.10148567878272127651418150057167370976237561540341534489730560694847754012391
Line 507, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_app/latest/run.log

  UVM_FATAL @ 1610983548 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (240 [0xf0] vs 127 [0x7f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1610983548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_burst_write has 3 failures.
  - 5.kmac_burst_write.40466573817424316437959849133268519303876025074297003376736935979019875671970
    Line 890, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.kmac_burst_write.40669834618085196600961440801179797999442455288668533419049003483743294368955
    Line 1208, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 15.kmac_shadow_reg_errors_with_csr_rw.29635973673418844033601193702252297684045664276432683997267987404999567622741
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  18134876 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1254286363 [0x4ac2e41b] vs 0 [0x0]) Regname: kmac_reg_block.prefix_8.prefix_0 reset value: 0x0
  UVM_INFO @  18134876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```