KMAC/UNMASKED Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.171m	13.168ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	53.906us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.290s	59.039us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.330s	2.550ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.440s	478.408us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.410s	259.332us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.290s	59.039us	20	20	100.00
		kmac_csr_aliasing	9.440s	478.408us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	12.478us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	37.687us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.662m	133.338ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.208m	55.477ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.162m	583.954ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.045m	1.595s	50	50	100.00
		kmac_test_vectors_sha3_384	26.552m	280.982ms	50	50	100.00
		kmac_test_vectors_sha3_512	20.352m	791.409ms	50	50	100.00
		kmac_test_vectors_shake_128	1.684h	2.857s	50	50	100.00
		kmac_test_vectors_shake_256	1.296h	752.320ms	50	50	100.00
		kmac_test_vectors_kmac	5.870s	2.117ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.670s	4.959ms	50	50	100.00
V2	sideload	kmac_sideload	7.596m	81.619ms	50	50	100.00
V2	app	kmac_app	6.284m	38.917ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.596m	37.687ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.646m	21.787ms	49	50	98.00
V2	error	kmac_error	6.826m	35.562ms	49	50	98.00
V2	key_error	kmac_key_error	7.670s	2.822ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.960s	7.190ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.260s	5.784ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.010m	14.643ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.550s	707.230us	50	50	100.00
V2	stress_all	kmac_stress_all	45.221m	202.782ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.800s	15.933us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	64.185us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.020s	490.511us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.020s	490.511us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	53.906us	5	5	100.00
		kmac_csr_rw	1.290s	59.039us	20	20	100.00
		kmac_csr_aliasing	9.440s	478.408us	5	5	100.00
		kmac_same_csr_outstanding	2.490s	390.860us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	53.906us	5	5	100.00
		kmac_csr_rw	1.290s	59.039us	20	20	100.00
		kmac_csr_aliasing	9.440s	478.408us	5	5	100.00
		kmac_same_csr_outstanding	2.490s	390.860us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.530s	106.768us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.530s	106.768us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.530s	106.768us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.530s	106.768us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.520s	200.028us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.050m	4.649ms	5	5	100.00
		kmac_tl_intg_err	4.990s	814.344us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.990s	814.344us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.550s	707.230us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.171m	13.168ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.596m	81.619ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.530s	106.768us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.050m	4.649ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.050m	4.649ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.050m	4.649ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.171m	13.168ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.550s	707.230us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.050m	4.649ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.005m	122.469ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.171m	13.168ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	40.141m	161.568ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			1246	1290	96.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.15	96.18	92.44	100.00	87.50	94.60	98.84	96.45

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
  • Test kmac_stress_all_with_rand_reset has 38 failures.

    • 1.kmac_stress_all_with_rand_reset.93207109609786657514072415375569607121996353846850988896286595284836783330200
      Line 425, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12878818451 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12878818451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.kmac_stress_all_with_rand_reset.98575524947351926651486932970434159919056279421248050176902768274480367209219
      Line 476, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17298824929 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17298824929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 36 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
  • Test kmac_stress_all_with_rand_reset has 3 failures.

    • 6.kmac_stress_all_with_rand_reset.8002390666310100515037011482236871002224879050064594045300432176640711333170
      Line 714, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 117968541743 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 117968541743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.kmac_stress_all_with_rand_reset.101149595550355691525650559354366647856741471069319209885914436688878263797326
      Line 1201, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 165620255994 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 165620255994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test kmac_error has 1 failures.

    • 12.kmac_error.39162274641313329523104077641072905829752676190510983877984509873732653565556
      Line 810, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_burst_write has 1 failures.

    • 41.kmac_burst_write.27302348917899708462590556646631617815448160305935178151399011124283980216388
      Line 1028, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_entropy_refresh has 1 failures.

    • 49.kmac_entropy_refresh.108328122313292712847741269920404023732417160054451722262058661026355881283066
      Line 940, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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