KMAC/UNMASKED Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.095m	4.134ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	59.405us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.310s	48.548us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.050s	2.541ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.230s	533.059us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.660s	393.822us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.310s	48.548us	20	20	100.00
		kmac_csr_aliasing	10.230s	533.059us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	21.478us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.470s	190.956us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.379m	436.440ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.412m	148.847ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.633m	201.870ms	50	50	100.00
		kmac_test_vectors_sha3_256	31.580m	96.012ms	50	50	100.00
		kmac_test_vectors_sha3_384	28.201m	973.811ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.671m	250.667ms	50	50	100.00
		kmac_test_vectors_shake_128	1.728h	3.662s	50	50	100.00
		kmac_test_vectors_shake_256	1.533h	3.143s	50	50	100.00
		kmac_test_vectors_kmac	6.080s	4.158ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.400s	3.420ms	50	50	100.00
V2	sideload	kmac_sideload	6.613m	131.997ms	50	50	100.00
V2	app	kmac_app	4.836m	42.727ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.351m	51.379ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.471m	175.228ms	50	50	100.00
V2	error	kmac_error	6.135m	4.961ms	50	50	100.00
V2	key_error	kmac_key_error	7.190s	1.415ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.170s	8.268ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.740s	5.183ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	43.340s	8.378ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	18.700s	6.867ms	50	50	100.00
V2	stress_all	kmac_stress_all	32.280m	106.057ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.810s	18.940us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	21.392us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.860s	88.677us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.860s	88.677us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	59.405us	5	5	100.00
		kmac_csr_rw	1.310s	48.548us	20	20	100.00
		kmac_csr_aliasing	10.230s	533.059us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	591.543us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	59.405us	5	5	100.00
		kmac_csr_rw	1.310s	48.548us	20	20	100.00
		kmac_csr_aliasing	10.230s	533.059us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	591.543us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	48.540us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	48.540us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	48.540us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	48.540us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.130s	633.036us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	54.200s	4.104ms	5	5	100.00
		kmac_tl_intg_err	5.250s	323.712us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.250s	323.712us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	18.700s	6.867ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.095m	4.134ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.613m	131.997ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	48.540us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.200s	4.104ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.200s	4.104ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.200s	4.104ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.095m	4.134ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	18.700s	6.867ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.200s	4.104ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.602m	55.587ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.095m	4.134ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	38.469m	225.751ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			1249	1290	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.58	96.12	92.34	100.00	90.91	94.52	98.84	96.31

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
  • Test kmac_stress_all_with_rand_reset has 35 failures.

    • 0.kmac_stress_all_with_rand_reset.87590118453168676155066141613562023059295830222008442675263029098251320548817
      Line 1393, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39351680823 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 39351680823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.32981566480095617093974207455578962877852070435995451887379882697883688698878
      Line 2588, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 363350676127 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 363350676127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 33 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
  • Test kmac_stress_all_with_rand_reset has 4 failures.

    • 23.kmac_stress_all_with_rand_reset.107966048441590497563313653224623739140299893913954018093979917545882683655253
      Line 761, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24455737601 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 24455737601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.kmac_stress_all_with_rand_reset.68987102532845058053710273075616330384178446250522085410993315677135490404623
      Line 1213, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5535151018 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 5535151018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test kmac_burst_write has 2 failures.

    • 4.kmac_burst_write.76897519773614174588964887900585238791783402338662049250289837654209827855247
      Line 802, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.kmac_burst_write.106470288412761074013229310891299730437959451471066269211535768815027288354733
      Line 1022, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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