KMAC/UNMASKED Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.138m	31.628ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.080s	44.342us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.270s	86.688us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.230s	994.436us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.870s	263.071us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.820s	77.088us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.270s	86.688us	20	20	100.00
		kmac_csr_aliasing	7.870s	263.071us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	52.682us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.420s	127.702us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	44.386m	755.262ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.685m	81.804ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	40.056m	1.245s	50	50	100.00
		kmac_test_vectors_sha3_256	36.838m	1.044s	50	50	100.00
		kmac_test_vectors_sha3_384	25.788m	289.141ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.509m	199.196ms	50	50	100.00
		kmac_test_vectors_shake_128	1.646h	3.396s	50	50	100.00
		kmac_test_vectors_shake_256	1.349h	1.278s	50	50	100.00
		kmac_test_vectors_kmac	5.900s	3.417ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.280s	998.605us	50	50	100.00
V2	sideload	kmac_sideload	7.549m	54.235ms	50	50	100.00
V2	app	kmac_app	5.813m	58.074ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.917m	27.766ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.839m	14.491ms	49	50	98.00
V2	error	kmac_error	7.096m	83.792ms	50	50	100.00
V2	key_error	kmac_key_error	7.450s	6.012ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.620s	1.922ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.900s	2.966ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.366m	87.631ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	33.480s	3.483ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.809m	125.771ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.830s	24.836us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	64.454us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.830s	142.714us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.830s	142.714us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.080s	44.342us	5	5	100.00
		kmac_csr_rw	1.270s	86.688us	20	20	100.00
		kmac_csr_aliasing	7.870s	263.071us	5	5	100.00
		kmac_same_csr_outstanding	2.640s	562.649us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.080s	44.342us	5	5	100.00
		kmac_csr_rw	1.270s	86.688us	20	20	100.00
		kmac_csr_aliasing	7.870s	263.071us	5	5	100.00
		kmac_same_csr_outstanding	2.640s	562.649us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.750s	135.261us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.750s	135.261us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.750s	135.261us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.750s	135.261us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.010s	514.723us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.097m	22.904ms	5	5	100.00
		kmac_tl_intg_err	5.360s	320.477us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.360s	320.477us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	33.480s	3.483ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.138m	31.628ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.549m	54.235ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.750s	135.261us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.097m	22.904ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.097m	22.904ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.097m	22.904ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.138m	31.628ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	33.480s	3.483ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.097m	22.904ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.911m	15.662ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.138m	31.628ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.389m	41.719ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			1242	1290	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.15	96.18	92.44	100.00	87.50	94.60	98.84	96.45

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test kmac_stress_all_with_rand_reset has 28 failures.
  - 3.kmac_stress_all_with_rand_reset.41190090962552210705708695159115088994597691972790275486101553931642904766773
    Line 290, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3176674009 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3176674009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.92963719376911093340417363300256629090775847328160447043548767198434287231814
    Line 2571, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 134546006077 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 134546006077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 15 failures:
- Test kmac_stress_all_with_rand_reset has 15 failures.
  - 8.kmac_stress_all_with_rand_reset.100200893052590130851613749243109429400245372880314709697338561315086826128437
    Line 488, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17344288517 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 17344288517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_stress_all_with_rand_reset.73779292425973116918048343753469675468660383942789986110486285319741686144561
    Line 1304, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21115218527 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 21115218527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 3 failures:

Test kmac_app has 3 failures.

6.kmac_app.109686547964523713064471649249555653461516291033169423263590196318003359421120
Line 559, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app/latest/run.log

  UVM_FATAL @ 31348932187 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (251 [0xfb] vs 160 [0xa0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 31348932187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.kmac_app.95925465993331370998572676026038766371100826722698919543979096597838717404430
Line 929, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_app/latest/run.log

  UVM_FATAL @ 14811341985 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (205 [0xcd] vs 0 [0x0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14811341985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 11.kmac_entropy_refresh.100139140882195412882288498986642541431132139152392368657396471244268802609782
    Line 800, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 21.kmac_burst_write.58427899064964809820004169820573501722805524738738991312424096969544501276955
    Line 860, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```