KMAC/UNMASKED Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.176m	7.462ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	32.044us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	28.052us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.320s	1.050ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.060s	139.420us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.900s	152.290us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	28.052us	20	20	100.00
		kmac_csr_aliasing	8.060s	139.420us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	13.007us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.380s	20.517us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.605m	415.639ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.143m	100.629ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.969m	402.543ms	50	50	100.00
		kmac_test_vectors_sha3_256	40.040m	1.810s	50	50	100.00
		kmac_test_vectors_sha3_384	26.084m	146.212ms	50	50	100.00
		kmac_test_vectors_sha3_512	20.602m	690.696ms	50	50	100.00
		kmac_test_vectors_shake_128	1.587h	1.068s	50	50	100.00
		kmac_test_vectors_shake_256	1.304h	1.083s	50	50	100.00
		kmac_test_vectors_kmac	5.560s	1.046ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.870s	1.218ms	50	50	100.00
V2	sideload	kmac_sideload	7.592m	84.213ms	50	50	100.00
V2	app	kmac_app	5.703m	101.228ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.923m	16.792ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.204m	17.740ms	49	50	98.00
V2	error	kmac_error	7.415m	39.938ms	50	50	100.00
V2	key_error	kmac_key_error	13.630s	16.757ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.420s	3.751ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.120s	1.602ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.382m	31.079ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.490s	3.376ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.328h	656.203ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.890s	19.220us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	95.961us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.140s	232.359us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.140s	232.359us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	32.044us	5	5	100.00
		kmac_csr_rw	1.230s	28.052us	20	20	100.00
		kmac_csr_aliasing	8.060s	139.420us	5	5	100.00
		kmac_same_csr_outstanding	2.730s	553.566us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	32.044us	5	5	100.00
		kmac_csr_rw	1.230s	28.052us	20	20	100.00
		kmac_csr_aliasing	8.060s	139.420us	5	5	100.00
		kmac_same_csr_outstanding	2.730s	553.566us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.410s	410.785us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.410s	410.785us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.410s	410.785us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.410s	410.785us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.780s	453.589us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	51.240s	21.145ms	5	5	100.00
		kmac_tl_intg_err	5.660s	1.192ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.660s	1.192ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.490s	3.376ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.176m	7.462ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.592m	84.213ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.410s	410.785us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	51.240s	21.145ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	51.240s	21.145ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	51.240s	21.145ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.176m	7.462ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.490s	3.376ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	51.240s	21.145ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.949m	27.015ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.176m	7.462ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	35.016m	92.832ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			1246	1290	96.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.19	95.88	92.30	100.00	67.77	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test kmac_stress_all_with_rand_reset has 34 failures.
  - 0.kmac_stress_all_with_rand_reset.92085058894556540914340427297973077264445004697540963304461207726624486880120
    Line 647, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 118934281725 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 118934281725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.66717570442630581767966430424381878304807891926940459471961666877449322633360
    Line 558, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25369876760 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25369876760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status

has 5 failures:

Test kmac_shadow_reg_errors has 2 failures.

5.kmac_shadow_reg_errors.82651384304900367771895565490977740812012653469307986466533555380382269373164
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  29991241 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  29991241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors.101952265827695982652250629899261346188054385805065508116686258765729618397792
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  59157284 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  59157284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

5.kmac_shadow_reg_errors_with_csr_rw.37285060841708915474360700464056584050650139963379014909881900418527011823063
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  57690745 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  57690745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_shadow_reg_errors_with_csr_rw.66939459665380268227677717731222033792321075807213774353429607803228439723306
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  10528173 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  10528173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 14.kmac_stress_all_with_rand_reset.24037309013701922215007579297470021605606261439087549736719320152182536709635
    Line 2505, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 92832147588 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 92832147588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.kmac_stress_all_with_rand_reset.47294800941486463540471390986835021381546895749011079982676119842164281655599
    Line 917, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20280860389 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 20280860389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_app has 1 failures.
  - 19.kmac_app.13432578407226898684908329364183540122814167425133160428217123937003974145949
    Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_app/latest/run.log
```
  UVM_FATAL @ 655448785 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (151 [0x97] vs 15 [0xf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 655448785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 21.kmac_entropy_refresh.113753180882120871885049240625858080664155935856741130424424835749993481612566
    Line 343, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 10497007563 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (110 [0x6e] vs 4 [0x4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10497007563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```