KMAC/UNMASKED Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.105m	10.793ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.940s	37.528us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.140s	52.890us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.580s	15.966ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.770s	943.197us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.620s	193.872us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.140s	52.890us	20	20	100.00
		kmac_csr_aliasing	5.770s	943.197us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	14.081us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	137.790us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.627m	260.115ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.525m	64.986ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.050m	1.396s	50	50	100.00
		kmac_test_vectors_sha3_256	32.408m	1.029s	50	50	100.00
		kmac_test_vectors_sha3_384	24.704m	302.263ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.108m	324.550ms	50	50	100.00
		kmac_test_vectors_shake_128	1.564h	2.791s	50	50	100.00
		kmac_test_vectors_shake_256	1.321h	1.001s	50	50	100.00
		kmac_test_vectors_kmac	5.420s	265.262us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.820s	1.599ms	50	50	100.00
V2	sideload	kmac_sideload	7.068m	21.849ms	50	50	100.00
V2	app	kmac_app	5.065m	79.328ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.466m	20.634ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.624m	123.381ms	50	50	100.00
V2	error	kmac_error	6.275m	12.240ms	49	50	98.00
V2	key_error	kmac_key_error	12.480s	25.982ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.260s	6.494ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.700s	4.379ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.113m	7.396ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.340s	1.650ms	50	50	100.00
V2	stress_all	kmac_stress_all	35.976m	213.160ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.830s	19.537us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	212.302us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.220s	144.812us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.220s	144.812us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.940s	37.528us	5	5	100.00
		kmac_csr_rw	1.140s	52.890us	20	20	100.00
		kmac_csr_aliasing	5.770s	943.197us	5	5	100.00
		kmac_same_csr_outstanding	2.550s	999.397us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.940s	37.528us	5	5	100.00
		kmac_csr_rw	1.140s	52.890us	20	20	100.00
		kmac_csr_aliasing	5.770s	943.197us	5	5	100.00
		kmac_same_csr_outstanding	2.550s	999.397us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.480s	80.986us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.480s	80.986us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.480s	80.986us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.480s	80.986us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.370s	2.342ms	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.174m	18.450ms	5	5	100.00
		kmac_tl_intg_err	5.180s	412.864us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.180s	412.864us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.340s	1.650ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.105m	10.793ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.068m	21.849ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.480s	80.986us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.174m	18.450ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.174m	18.450ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.174m	18.450ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.105m	10.793ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.340s	1.650ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.174m	18.450ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.997m	25.268ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.105m	10.793ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.648m	187.328ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			1241	1290	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.21	95.88	92.30	100.00	67.77	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test kmac_stress_all_with_rand_reset has 34 failures.
  - 0.kmac_stress_all_with_rand_reset.83918112199321588315253668773132038703078071815033453671403223998426231793705
    Line 696, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 178511059625 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 178511059625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.3599545089151665959032581860454852066867712255298859080940120385965533019096
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 602712813 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 602712813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 4.kmac_stress_all_with_rand_reset.54136553746278345179259778556575195604473424025981464417171048012944444487571
    Line 2025, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 187328477585 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 187328477585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.55202283497748078616306141527016158294686538966306829943652948883283740542758
    Line 910, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20637342091 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 20637342091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

2.kmac_shadow_reg_errors_with_csr_rw.107313769863957681296168459853441837604915283890335468800344700352487907521465
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 277651081 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 277651081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 3 failures.

12.kmac_shadow_reg_errors.105490995544547621396096058905510899956081320897480565450705785443117588759339
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   6098549 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   6098549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_shadow_reg_errors.55017066002008662264236575705130574470779740595661283009968105653539713732104
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   4261492 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   4261492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_mubi has 1 failures.

7.kmac_mubi.18694867023717105947898750376495645879636967404793543369818203412360693536198
Line 639, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_mubi/latest/run.log

  UVM_FATAL @ 8325452452 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (16 [0x10] vs 58 [0x3a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8325452452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

16.kmac_stress_all.88186307902932852774078319907335678146853488325162647581156952174068175774995
Line 1209, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest/run.log

  UVM_FATAL @ 45485240114 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (168 [0xa8] vs 225 [0xe1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 45485240114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.kmac_stress_all.42712549945042973940408262494650363932245377201561403956154284073893030905481
Line 329, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest/run.log

  UVM_FATAL @ 6669507075 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (43 [0x2b] vs 121 [0x79]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6669507075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 31.kmac_error.100218412885937572401822787581392414415624964613147868127794151152210136664074
    Line 1010, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```