KMAC/UNMASKED Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.105m 10.793ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 0.940s 37.528us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.140s 52.890us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 22.580s 15.966ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 5.770s 943.197us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.620s 193.872us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.140s 52.890us 20 20 100.00
kmac_csr_aliasing 5.770s 943.197us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.720s 14.081us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.480s 137.790us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 47.627m 260.115ms 50 50 100.00
V2 burst_write kmac_burst_write 12.525m 64.986ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 35.050m 1.396s 50 50 100.00
kmac_test_vectors_sha3_256 32.408m 1.029s 50 50 100.00
kmac_test_vectors_sha3_384 24.704m 302.263ms 50 50 100.00
kmac_test_vectors_sha3_512 18.108m 324.550ms 50 50 100.00
kmac_test_vectors_shake_128 1.564h 2.791s 50 50 100.00
kmac_test_vectors_shake_256 1.321h 1.001s 50 50 100.00
kmac_test_vectors_kmac 5.420s 265.262us 50 50 100.00
kmac_test_vectors_kmac_xof 5.820s 1.599ms 50 50 100.00
V2 sideload kmac_sideload 7.068m 21.849ms 50 50 100.00
V2 app kmac_app 5.065m 79.328ms 50 50 100.00
V2 app_with_partial_data kmac_app_with_partial_data 5.466m 20.634ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 5.624m 123.381ms 50 50 100.00
V2 error kmac_error 6.275m 12.240ms 49 50 98.00
V2 key_error kmac_key_error 12.480s 25.982ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 46.260s 6.494ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 43.700s 4.379ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.113m 7.396ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 37.340s 1.650ms 50 50 100.00
V2 stress_all kmac_stress_all 35.976m 213.160ms 48 50 96.00
V2 intr_test kmac_intr_test 0.830s 19.537us 50 50 100.00
V2 alert_test kmac_alert_test 0.910s 212.302us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.220s 144.812us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.220s 144.812us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 0.940s 37.528us 5 5 100.00
kmac_csr_rw 1.140s 52.890us 20 20 100.00
kmac_csr_aliasing 5.770s 943.197us 5 5 100.00
kmac_same_csr_outstanding 2.550s 999.397us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 0.940s 37.528us 5 5 100.00
kmac_csr_rw 1.140s 52.890us 20 20 100.00
kmac_csr_aliasing 5.770s 943.197us 5 5 100.00
kmac_same_csr_outstanding 2.550s 999.397us 20 20 100.00
V2 TOTAL 1047 1050 99.71
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.480s 80.986us 17 20 85.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.480s 80.986us 17 20 85.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.480s 80.986us 17 20 85.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.480s 80.986us 17 20 85.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.370s 2.342ms 19 20 95.00
V2S tl_intg_err kmac_sec_cm 1.174m 18.450ms 5 5 100.00
kmac_tl_intg_err 5.180s 412.864us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.180s 412.864us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 37.340s 1.650ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.105m 10.793ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 7.068m 21.849ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.480s 80.986us 17 20 85.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.174m 18.450ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.174m 18.450ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.174m 18.450ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.105m 10.793ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 37.340s 1.650ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.174m 18.450ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 4.997m 25.268ms 9 10 90.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.105m 10.793ms 50 50 100.00
V2S TOTAL 70 75 93.33
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 31.648m 187.328ms 9 50 18.00
V3 TOTAL 9 50 18.00
TOTAL 1241 1290 96.20

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 23 92.00
V2S 5 5 2 40.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.21 95.88 92.30 100.00 67.77 94.11 98.84 96.58

Failure Buckets

Past Results