KMAC/UNMASKED Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.268m	15.990ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	121.926us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	246.521us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.940s	1.575ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.660s	762.100us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.680s	520.577us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	246.521us	20	20	100.00
		kmac_csr_aliasing	9.660s	762.100us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	13.114us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.570s	53.317us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.781m	92.799ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.998m	69.968ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.674m	103.063ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.098m	384.891ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.666m	664.104ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.958m	101.967ms	50	50	100.00
		kmac_test_vectors_shake_128	1.658h	1.728s	50	50	100.00
		kmac_test_vectors_shake_256	1.352h	906.653ms	50	50	100.00
		kmac_test_vectors_kmac	5.730s	1.937ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.380s	246.491us	50	50	100.00
V2	sideload	kmac_sideload	6.859m	28.175ms	50	50	100.00
V2	app	kmac_app	5.387m	58.461ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.953m	58.729ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.365m	61.771ms	48	50	96.00
V2	error	kmac_error	7.348m	105.068ms	49	50	98.00
V2	key_error	kmac_key_error	18.530s	33.613ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.050s	9.367ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.590s	5.850ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.026m	5.296ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.560s	3.321ms	50	50	100.00
V2	stress_all	kmac_stress_all	36.941m	75.875ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.890s	16.538us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	23.523us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.390s	571.247us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.390s	571.247us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	121.926us	5	5	100.00
		kmac_csr_rw	1.200s	246.521us	20	20	100.00
		kmac_csr_aliasing	9.660s	762.100us	5	5	100.00
		kmac_same_csr_outstanding	2.540s	798.314us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	121.926us	5	5	100.00
		kmac_csr_rw	1.200s	246.521us	20	20	100.00
		kmac_csr_aliasing	9.660s	762.100us	5	5	100.00
		kmac_same_csr_outstanding	2.540s	798.314us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.420s	212.545us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.420s	212.545us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.420s	212.545us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.420s	212.545us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.880s	137.669us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.117m	12.381ms	5	5	100.00
		kmac_tl_intg_err	5.110s	504.452us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.110s	504.452us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.560s	3.321ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.268m	15.990ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.859m	28.175ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.420s	212.545us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.117m	12.381ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.117m	12.381ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.117m	12.381ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.268m	15.990ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.560s	3.321ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.117m	12.381ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.821m	16.843ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.268m	15.990ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	46.594m	416.140ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			1238	1290	95.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.18	95.88	92.26	100.00	67.77	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test kmac_stress_all_with_rand_reset has 37 failures.
  - 0.kmac_stress_all_with_rand_reset.103506650023301495588459221364624518988385671910568063041069548217211532248752
    Line 354, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26853066248 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26853066248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.13754087246783204104067509290965872961842567688719444127793934653895360572135
    Line 484, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30345933834 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30345933834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

1.kmac_shadow_reg_errors_with_csr_rw.100744143832445204883966301275553188252510245106261267070323208127346191809886
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  28086661 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  28086661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.54947028395975763323673091555797768354545220452692139270396887846513550284562
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 212736743 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 212736743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors has 1 failures.

19.kmac_shadow_reg_errors.14489504371647774737069047358279872202706340588653758727656047726327052130760
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  76540276 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  76540276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app_with_partial_data has 1 failures.

6.kmac_app_with_partial_data.2848410079413214008485834512307001740354539247628937686097391552397931482360
Line 555, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 12883460188 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (178 [0xb2] vs 211 [0xd3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12883460188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

12.kmac_entropy_refresh.109653092219881992967349087690682302042620701158231221747188510425470903159657
Line 413, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 15042944295 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (25 [0x19] vs 81 [0x51]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 15042944295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.kmac_entropy_refresh.100362467559641599484068237986924158253038766619666343173569375077544229546753
Line 467, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 4800894494 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (209 [0xd1] vs 127 [0x7f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4800894494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

19.kmac_stress_all_with_rand_reset.3954099947043712298693659094765332339036854193907333865125627914128013569059
Line 949, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 5538024628 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (212 [0xd4] vs 215 [0xd7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5538024628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 2.kmac_stress_all_with_rand_reset.32982572133446972271844951592292807311816033695009884111044914965199338685026
    Line 1619, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31066023302 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 31066023302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.kmac_stress_all_with_rand_reset.89902828071474861607257770385270859411401350707271030891574800520519436829068
    Line 1070, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 74668950564 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 74668950564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_burst_write has 1 failures.
  - 20.kmac_burst_write.61743976473326704277337908212561333972676391502013599538210904743794973360257
    Line 590, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app has 1 failures.
  - 25.kmac_app.57676207050322947692309105058588865293874156852825407739283023366993196732931
    Line 883, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 49.kmac_error.7572992039727166950959633551164016769998033891195987762556322337614577188611
    Line 777, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```