KMAC/UNMASKED Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.044m	2.713ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	35.251us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	33.221us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.500s	2.041ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.950s	2.179ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.550s	41.714us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	33.221us	20	20	100.00
		kmac_csr_aliasing	9.950s	2.179ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	20.303us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.600s	41.609us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.314m	845.226ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.220m	34.249ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.194m	390.948ms	50	50	100.00
		kmac_test_vectors_sha3_256	37.603m	932.518ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.592m	697.398ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.277m	99.740ms	50	50	100.00
		kmac_test_vectors_shake_128	1.600h	1.296s	50	50	100.00
		kmac_test_vectors_shake_256	1.469h	2.421s	50	50	100.00
		kmac_test_vectors_kmac	5.330s	189.356us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.650s	509.243us	50	50	100.00
V2	sideload	kmac_sideload	7.606m	21.418ms	50	50	100.00
V2	app	kmac_app	4.941m	13.158ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.196m	61.260ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.967m	20.198ms	50	50	100.00
V2	error	kmac_error	6.850m	38.748ms	50	50	100.00
V2	key_error	kmac_key_error	9.590s	10.105ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.910s	2.069ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.120s	2.108ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.154m	52.256ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	25.480s	1.051ms	50	50	100.00
V2	stress_all	kmac_stress_all	42.680m	465.898ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.900s	18.791us	50	50	100.00
V2	alert_test	kmac_alert_test	0.850s	30.059us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.030s	599.336us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.030s	599.336us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	35.251us	5	5	100.00
		kmac_csr_rw	1.230s	33.221us	20	20	100.00
		kmac_csr_aliasing	9.950s	2.179ms	5	5	100.00
		kmac_same_csr_outstanding	2.800s	1.107ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	35.251us	5	5	100.00
		kmac_csr_rw	1.230s	33.221us	20	20	100.00
		kmac_csr_aliasing	9.950s	2.179ms	5	5	100.00
		kmac_same_csr_outstanding	2.800s	1.107ms	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.310s	45.347us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.310s	45.347us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.310s	45.347us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.310s	45.347us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.250s	645.089us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.274m	42.847ms	5	5	100.00
		kmac_tl_intg_err	5.190s	484.498us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.190s	484.498us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	25.480s	1.051ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.044m	2.713ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.606m	21.418ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.310s	45.347us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.274m	42.847ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.274m	42.847ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.274m	42.847ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.044m	2.713ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	25.480s	1.051ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.274m	42.847ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.531m	46.878ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.044m	2.713ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.638m	123.763ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			1236	1290	95.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.46	95.88	92.26	100.00	69.42	94.11	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test kmac_stress_all_with_rand_reset has 29 failures.
  - 0.kmac_stress_all_with_rand_reset.80325886560960342131481885570553688887133024738191778958362576925997263743637
    Line 427, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25951124695 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25951124695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.16593276975415275767912118292803558893781538707440165209907869571939255200376
    Line 902, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65987673327 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 65987673327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 11 failures:
- Test kmac_stress_all_with_rand_reset has 11 failures.
  - 3.kmac_stress_all_with_rand_reset.1491780067880482550868138399507212497258907186493855044360581631194383743967
    Line 836, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 115690068563 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 115690068563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.73049293516261501880325250350598996878356281701637989891768306914766668874587
    Line 2087, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53505472413 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 53505472413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 7 failures:

Test kmac_shadow_reg_errors has 3 failures.

1.kmac_shadow_reg_errors.93772894133157136738185074117685654592318588162290986362733682016999162884991
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  13687428 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  13687428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors.71960513040570775017118732125668826046924515909398261954097655752646611039083
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  11812602 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  11812602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

7.kmac_shadow_reg_errors_with_csr_rw.67879166667775935502125259717893466245511661871894965162351732699188466262449
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  49854343 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  49854343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors_with_csr_rw.40147507716221732532266927701508003032772320422701118943961048727845627584386
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 111894793 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 111894793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 3 failures.

2.kmac_app.57631462856950977369577964109203816330203684477155590477417740095319861450051
Line 471, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_app/latest/run.log

  UVM_FATAL @ 6562668198 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (13 [0xd] vs 223 [0xdf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6562668198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_app.86037078571708569313593807287151489823382863735560952355645761701654724181022
Line 557, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_app/latest/run.log

  UVM_FATAL @ 10439684484 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (137 [0x89] vs 53 [0x35]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10439684484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_stress_all has 1 failures.

48.kmac_stress_all.14060644831165730308320106896103175879737019105570263321039523630525296537494
Line 465, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest/run.log

  UVM_FATAL @ 18299067696 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (103 [0x67] vs 49 [0x31]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 18299067696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 22.kmac_burst_write.55438121845343749938621726827328710866136199616808320775639197702817228599263
    Line 1208, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 22.kmac_stress_all_with_rand_reset.20497845502858915632856482046091334980457808285462028621039890886764026667590
    Line 470, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9306421662 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (205 [0xcd] vs 115 [0x73]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 9306421662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 24.kmac_key_error.97283093185125464233837707040666704435864933050659961027123790586864066154386
    Line 271, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 3786052951 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 3786052951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```