KMAC/UNMASKED Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.197m	29.304ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.090s	289.132us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	30.186us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.950s	2.869ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.480s	1.527ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.760s	340.352us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	30.186us	20	20	100.00
		kmac_csr_aliasing	9.480s	1.527ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	13.945us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.580s	165.051us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.023m	264.538ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.776m	35.638ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.914m	398.355ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.579m	694.330ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.633m	289.904ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.783m	201.849ms	50	50	100.00
		kmac_test_vectors_shake_128	1.616h	996.584ms	50	50	100.00
		kmac_test_vectors_shake_256	1.326h	797.358ms	50	50	100.00
		kmac_test_vectors_kmac	5.300s	248.372us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.760s	3.533ms	50	50	100.00
V2	sideload	kmac_sideload	7.967m	281.095ms	50	50	100.00
V2	app	kmac_app	5.469m	23.302ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.413m	10.342ms	8	10	80.00
V2	entropy_refresh	kmac_entropy_refresh	5.585m	40.717ms	50	50	100.00
V2	error	kmac_error	6.444m	110.714ms	50	50	100.00
V2	key_error	kmac_key_error	10.040s	8.980ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.700s	9.002ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	27.040s	1.118ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.298m	33.405ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	36.890s	1.731ms	50	50	100.00
V2	stress_all	kmac_stress_all	42.551m	374.868ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	34.548us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	75.466us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.900s	97.411us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.900s	97.411us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.090s	289.132us	5	5	100.00
		kmac_csr_rw	1.190s	30.186us	20	20	100.00
		kmac_csr_aliasing	9.480s	1.527ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	422.064us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.090s	289.132us	5	5	100.00
		kmac_csr_rw	1.190s	30.186us	20	20	100.00
		kmac_csr_aliasing	9.480s	1.527ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	422.064us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.410s	75.768us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.410s	75.768us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.410s	75.768us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.410s	75.768us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.990s	430.645us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.199m	5.372ms	5	5	100.00
		kmac_tl_intg_err	5.530s	2.710ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.530s	2.710ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	36.890s	1.731ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.197m	29.304ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.967m	281.095ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.410s	75.768us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.199m	5.372ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.199m	5.372ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.199m	5.372ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.197m	29.304ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	36.890s	1.731ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.199m	5.372ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.784m	44.345ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.197m	29.304ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	42.717m	329.833ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			1235	1290	95.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.37	95.91	92.33	100.00	68.60	94.19	99.00	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
- Test kmac_stress_all_with_rand_reset has 38 failures.
  - 0.kmac_stress_all_with_rand_reset.59699298264403734967158321224907375857005665727085405297920614035926503753101
    Line 418, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 193589831091 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 193589831091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.85177211955440069641375822919035860324343706031414784176331707715895373862151
    Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 373125143 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 373125143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 36 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 5.kmac_stress_all_with_rand_reset.35437912451134882027508848011635224879321677296339984368320485002831913177971
    Line 470, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8300698023 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 8300698023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.kmac_stress_all_with_rand_reset.69307944423632608365226336799029994005202379286520562622819907264053033243884
    Line 986, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10681312655 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 10681312655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

1.kmac_shadow_reg_errors_with_csr_rw.46841986779311986931092021256611444391272193256054248791374815006012460629066
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  71836903 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  71836903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors_with_csr_rw.68024916671399044118384470470298642402218451961450730393896693797476396766366
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  98085417 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  98085417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors has 1 failures.

13.kmac_shadow_reg_errors.107136444568309719656432065104130912854821204785345609984041280521004090403324
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  22466971 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  22466971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app_with_partial_data has 1 failures.

0.kmac_app_with_partial_data.97514988386037994949618499958469119477172747293576744452598842544556446995934
Line 719, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 29877350457 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (127 [0x7f] vs 226 [0xe2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 29877350457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

6.kmac_stress_all.82521137270637497138150240520172598023136933032860756127031031851331493156173
Line 1549, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest/run.log

  UVM_FATAL @ 157034169271 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (247 [0xf7] vs 231 [0xe7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 157034169271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

43.kmac_app.59142191851541271446647734246161217130818030270036579156968768076378565454491
Line 617, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_app/latest/run.log

  UVM_FATAL @ 4977667248 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (143 [0x8f] vs 228 [0xe4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4977667248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 9.kmac_burst_write.81745327613586799007217175231127681485452475123956674430319948974406053796348
    Line 549, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.kmac_burst_write.35390243324372349516905037256017870153348948861532555378403113491718271071030
    Line 710, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.cfg_regwen has 1 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 6.kmac_app_with_partial_data.58911206019177315936912619135745089612777512440986565074749289388976580188689
    Line 332, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log
```
  UVM_ERROR @ 2435640001 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: kmac_reg_block.cfg_regwen
  UVM_INFO @ 2435640001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```