KMAC/UNMASKED Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.136m	4.106ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	42.228us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	33.177us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.190s	285.101us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.540s	2.015ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.500s	330.554us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	33.177us	20	20	100.00
		kmac_csr_aliasing	9.540s	2.015ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	13.439us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	146.181us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.144m	520.883ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.297m	123.114ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.164m	1.201s	50	50	100.00
		kmac_test_vectors_sha3_256	33.707m	184.861ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.842m	72.077ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.760m	813.573ms	50	50	100.00
		kmac_test_vectors_shake_128	1.755h	4.303s	50	50	100.00
		kmac_test_vectors_shake_256	1.233h	1.038s	50	50	100.00
		kmac_test_vectors_kmac	6.000s	2.003ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.370s	1.000ms	50	50	100.00
V2	sideload	kmac_sideload	7.232m	83.133ms	50	50	100.00
V2	app	kmac_app	4.940m	16.143ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.312m	15.233ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.188m	12.925ms	50	50	100.00
V2	error	kmac_error	6.641m	20.153ms	48	50	96.00
V2	key_error	kmac_key_error	10.540s	8.521ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.550s	9.975ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.550s	2.045ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.109m	33.261ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	40.350s	755.946us	50	50	100.00
V2	stress_all	kmac_stress_all	35.442m	92.344ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.830s	17.529us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	34.688us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.930s	1.175ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.930s	1.175ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	42.228us	5	5	100.00
		kmac_csr_rw	1.220s	33.177us	20	20	100.00
		kmac_csr_aliasing	9.540s	2.015ms	5	5	100.00
		kmac_same_csr_outstanding	2.810s	486.384us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	42.228us	5	5	100.00
		kmac_csr_rw	1.220s	33.177us	20	20	100.00
		kmac_csr_aliasing	9.540s	2.015ms	5	5	100.00
		kmac_same_csr_outstanding	2.810s	486.384us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.470s	53.499us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.470s	53.499us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.470s	53.499us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.470s	53.499us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.930s	436.382us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	59.570s	9.075ms	5	5	100.00
		kmac_tl_intg_err	6.270s	4.053ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.270s	4.053ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	40.350s	755.946us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.136m	4.106ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.232m	83.133ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.470s	53.499us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	59.570s	9.075ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	59.570s	9.075ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	59.570s	9.075ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.136m	4.106ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	40.350s	755.946us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	59.570s	9.075ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.990m	44.792ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.136m	4.106ms	50	50	100.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.079h	2.787s	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			1242	1290	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.56	95.88	92.30	100.00	70.25	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test kmac_stress_all_with_rand_reset has 34 failures.
  - 1.kmac_stress_all_with_rand_reset.98844200769417918832130686179748579580906923459711934980969186678476728314080
    Line 1143, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15876530555 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15876530555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.64389019644118351562249744232021875904983779401145109515920783571276556878695
    Line 270, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 497025592 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 497025592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 2.kmac_stress_all_with_rand_reset.76761260389711108644547011707045156943008775086387514737659499297200378888682
    Line 779, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153063378861 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 153063378861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.kmac_stress_all_with_rand_reset.79347294245111698103154927741927040022572271400157248262216198680962815814230
    Line 1003, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 103664879662 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 103664879662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:

Test kmac_shadow_reg_errors has 1 failures.

1.kmac_shadow_reg_errors.106490688287855589268937822433402698206686211072748146646188622227934923261409
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  83655761 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  83655761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

13.kmac_shadow_reg_errors_with_csr_rw.109475440995260606395226501393259868732497010657292940082555462504850656566047
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  53923890 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  53923890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.kmac_shadow_reg_errors_with_csr_rw.20209858802401037327329825562381280353794237764889635061622159946132771155705
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  26620032 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  26620032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_burst_write has 1 failures.
  - 18.kmac_burst_write.83988279974371334461619642975924751922208338886537498682327666947576088723424
    Line 1190, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app has 1 failures.
  - 19.kmac_app.64815530869456079406986613460704972784957525667541787771423820005555396624315
    Line 822, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 31.kmac_error.34645984874655589030003113819344989151061440808542985408785784322579960591492
    Line 1092, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_app has 1 failures.

17.kmac_app.36160892136652879355139562901306125022287848643122399685933901312337855212587
Line 921, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_app/latest/run.log

  UVM_FATAL @ 12421958010 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (1 [0x1] vs 54 [0x36]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12421958010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

32.kmac_error.3734300356238895200778439975485910396930691790172223544690691374325251789036
Line 332, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_error/latest/run.log

  UVM_FATAL @ 1713805872 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (218 [0xda] vs 225 [0xe1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1713805872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 19.kmac_shadow_reg_errors_with_csr_rw.36985737741701263349421562783035558368986165612997824127182454456819735675325
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  46397844 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3607320121 [0xd7035639] vs 0 [0x0]) Regname: kmac_reg_block.prefix_3.prefix_0 reset value: 0x0
  UVM_INFO @  46397844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```