KMAC/UNMASKED Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.129m	4.170ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.050s	21.002us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	31.151us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.130s	972.566us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.170s	571.127us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.620s	531.500us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	31.151us	20	20	100.00
		kmac_csr_aliasing	8.170s	571.127us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	23.725us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	123.808us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.752m	526.052ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.512m	134.382ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.675m	100.231ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.989m	387.237ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.054m	488.206ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.940m	102.650ms	50	50	100.00
		kmac_test_vectors_shake_128	1.632h	2.119s	50	50	100.00
		kmac_test_vectors_shake_256	1.366h	2.453s	50	50	100.00
		kmac_test_vectors_kmac	6.140s	3.866ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.710s	1.057ms	50	50	100.00
V2	sideload	kmac_sideload	7.350m	199.414ms	50	50	100.00
V2	app	kmac_app	5.112m	24.177ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.535m	16.764ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.636m	52.646ms	49	50	98.00
V2	error	kmac_error	6.711m	102.726ms	49	50	98.00
V2	key_error	kmac_key_error	9.650s	7.813ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.590s	2.222ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.920s	7.307ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.270m	121.781ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.140s	7.082ms	50	50	100.00
V2	stress_all	kmac_stress_all	36.297m	208.496ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.880s	42.341us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	179.245us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.360s	534.848us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.360s	534.848us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.050s	21.002us	5	5	100.00
		kmac_csr_rw	1.180s	31.151us	20	20	100.00
		kmac_csr_aliasing	8.170s	571.127us	5	5	100.00
		kmac_same_csr_outstanding	2.600s	347.612us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.050s	21.002us	5	5	100.00
		kmac_csr_rw	1.180s	31.151us	20	20	100.00
		kmac_csr_aliasing	8.170s	571.127us	5	5	100.00
		kmac_same_csr_outstanding	2.600s	347.612us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	81.474us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	81.474us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	81.474us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	81.474us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.890s	120.810us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.014m	15.291ms	5	5	100.00
		kmac_tl_intg_err	4.800s	733.689us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.800s	733.689us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.140s	7.082ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.129m	4.170ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.350m	199.414ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	81.474us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.014m	15.291ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.014m	15.291ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.014m	15.291ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.129m	4.170ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.140s	7.082ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.014m	15.291ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.820m	30.032ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.129m	4.170ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	56.152m	205.773ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			1237	1290	95.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.30	95.88	92.27	100.00	68.60	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test kmac_stress_all_with_rand_reset has 34 failures.
  - 0.kmac_stress_all_with_rand_reset.114718522997092554032575427449499760706858550339692298726135420962606635837958
    Line 711, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 72497421951 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 72497421951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.32528563426932174993936589646329981323566584193196026187988730887638135948726
    Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 635184096 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 635184096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

0.kmac_shadow_reg_errors_with_csr_rw.37608474522859469040132395284015494215151959254777981861174731796113788526647
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  31632489 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  31632489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors_with_csr_rw.38692328123314573276944934573012795454914026508616421246671031666548655753957
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 164982572 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 164982572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors has 3 failures.

2.kmac_shadow_reg_errors.5794465264647643936138249326193491304642187496507438565542015981694066921731
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  44837926 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  44837926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_shadow_reg_errors.76158297849417804282225702622891272210204925943341599297582031956205147429657
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  18057246 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  18057246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 22.kmac_stress_all_with_rand_reset.73536535905215071938106773796493102091805716114094500498749559835112537649033
    Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21082791841 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 21082791841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.kmac_stress_all_with_rand_reset.90368559085034748148947141345578407294633109575861081356757622974465890411049
    Line 3099, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 674681506355 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 674681506355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all_with_rand_reset has 1 failures.

14.kmac_stress_all_with_rand_reset.7289954794795319471016056395260652356212278337810413149033980688046123870329
Line 707, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 9434362389 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (146 [0x92] vs 206 [0xce]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9434362389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

17.kmac_entropy_refresh.5782020526941294027576621490695160826723055778167941405783144639881957252759
Line 491, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 22265916773 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (61 [0x3d] vs 193 [0xc1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 22265916773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

24.kmac_app.90661634907534038990113914263505112066725000646297989002983973010451300112319
Line 901, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_app/latest/run.log

  UVM_FATAL @ 4077042529 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (63 [0x3f] vs 124 [0x7c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4077042529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.kmac_app.81286154177166119204762826454229887690147014881773493550656583473542454991847
Line 473, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_app/latest/run.log

  UVM_FATAL @ 11957893081 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (154 [0x9a] vs 178 [0xb2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11957893081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
- Test kmac_key_error has 1 failures.
  - 1.kmac_key_error.71369605805297729772372209459594282741025897073918146012337446836312243804201
    Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_key_error/latest/run.log
```
  UVM_ERROR @  39946311 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
  UVM_INFO @  39946311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 10.kmac_shadow_reg_errors_with_csr_rw.51036721789115702544567777252221068096827178375658769819199575933502349189723
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  17682806 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2857538568 [0xaa529408] vs 1194716467 [0x4735ed33]) Regname: kmac_reg_block.prefix_5.prefix_0 reset value: 0x0
  UVM_INFO @  17682806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 25.kmac_error.86969119872287714780593779841501798934020855793227626653356554995053344173473
    Line 910, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 47.kmac_stress_all_with_rand_reset.79265880288083970472670287979173280675343980774382971163284925455331745043465
    Line 1113, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 61806828997 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (59 [0x3b] vs 255 [0xff]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 61806828997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```