KMAC/UNMASKED Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.168m	30.057ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.080s	31.059us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	71.063us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.010s	1.495ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.260s	395.249us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.600s	74.661us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	71.063us	20	20	100.00
		kmac_csr_aliasing	9.260s	395.249us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	13.236us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	47.320us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.948m	111.334ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.219m	160.523ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.288m	1.072s	50	50	100.00
		kmac_test_vectors_sha3_256	34.874m	417.929ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.628m	773.797ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.497m	197.132ms	50	50	100.00
		kmac_test_vectors_shake_128	1.870h	3.250s	50	50	100.00
		kmac_test_vectors_shake_256	1.339h	871.044ms	50	50	100.00
		kmac_test_vectors_kmac	6.210s	4.244ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.460s	3.058ms	50	50	100.00
V2	sideload	kmac_sideload	7.104m	24.174ms	50	50	100.00
V2	app	kmac_app	5.381m	16.860ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.678m	75.233ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.619m	44.139ms	48	50	96.00
V2	error	kmac_error	7.371m	22.891ms	50	50	100.00
V2	key_error	kmac_key_error	11.740s	18.283ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.590s	15.631ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.410s	1.671ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.008m	54.941ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.130s	2.348ms	50	50	100.00
V2	stress_all	kmac_stress_all	33.633m	409.505ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.920s	16.199us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	25.599us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.570s	2.544ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.570s	2.544ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.080s	31.059us	5	5	100.00
		kmac_csr_rw	1.190s	71.063us	20	20	100.00
		kmac_csr_aliasing	9.260s	395.249us	5	5	100.00
		kmac_same_csr_outstanding	2.580s	249.627us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.080s	31.059us	5	5	100.00
		kmac_csr_rw	1.190s	71.063us	20	20	100.00
		kmac_csr_aliasing	9.260s	395.249us	5	5	100.00
		kmac_same_csr_outstanding	2.580s	249.627us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.420s	31.664us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.420s	31.664us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.420s	31.664us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.420s	31.664us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.330s	296.206us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	47.850s	6.086ms	5	5	100.00
		kmac_tl_intg_err	5.330s	283.296us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.330s	283.296us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.130s	2.348ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.168m	30.057ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.104m	24.174ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.420s	31.664us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	47.850s	6.086ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	47.850s	6.086ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	47.850s	6.086ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.168m	30.057ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.130s	2.348ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	47.850s	6.086ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.158m	7.123ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.168m	30.057ms	50	50	100.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.816m	71.201ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			1237	1290	95.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.15	95.88	92.30	100.00	67.77	94.11	98.84	96.15

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test kmac_stress_all_with_rand_reset has 34 failures.
  - 3.kmac_stress_all_with_rand_reset.3710804951742582545016666509381478844207374162047284601143962549957285452645
    Line 1517, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43321419433 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 43321419433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.76427576549087888262279503247737012185538186037651130367453694153798565258528
    Line 309, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1514722755 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1514722755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.56422731190575382789506169702980263307575217576367580333825631572111294567562
    Line 1078, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47284139505 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 47284139505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.82567953511990609347378878242750665104494795364763518929052167201724267984410
    Line 866, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36854659186 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 36854659186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

1.kmac_shadow_reg_errors_with_csr_rw.46410037036049839027698636222763295134595380929439690549041856647721910607964
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  14938644 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  14938644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_shadow_reg_errors_with_csr_rw.79309225794606260200175644682093160512161416985747849408986641917306378180817
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 132971843 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 132971843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors has 2 failures.

8.kmac_shadow_reg_errors.13962877621076499112482986096754438502351034800763163355628813556383116611903
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  43956180 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  43956180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.kmac_shadow_reg_errors.109687511868784856206903283884671556055330798507356457507681388498931441317532
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   4400461 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   4400461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_mubi has 1 failures.

4.kmac_mubi.98187927421568046637776470950905128777211589350873908993676413530850244317635
Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_mubi/latest/run.log

  UVM_FATAL @ 945558582 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (183 [0xb7] vs 136 [0x88]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 945558582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

13.kmac_app.72103548891984799294018042425813415053107008026999048843472923854548766687927
Line 825, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_app/latest/run.log

  UVM_FATAL @ 2753593008 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (65 [0x41] vs 57 [0x39]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2753593008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_app.67407038276837573810411432038167572460198221529403583417187849159332031292971
Line 709, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_app/latest/run.log

  UVM_FATAL @ 10257884777 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (116 [0x74] vs 150 [0x96]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10257884777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

37.kmac_entropy_refresh.47353393514445021080938223837026692413643495820593309895105192282059623513336
Line 365, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 9508373800 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (36 [0x24] vs 167 [0xa7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9508373800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_entropy_refresh.26002634439580129240470890753588263874200303714634414858974600190205697334579
Line 553, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6169009899 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (188 [0xbc] vs 117 [0x75]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6169009899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_app has 1 failures.
  - 17.kmac_app.90144105888558234285724623052803544859329951970639209033873780465475543690912
    Line 1118, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```