KMAC/UNMASKED Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.165m	16.069ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	18.786us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	34.492us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.120s	1.533ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.740s	546.416us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.520s	84.913us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	34.492us	20	20	100.00
		kmac_csr_aliasing	9.740s	546.416us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	12.844us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	66.541us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	43.737m	1.530s	50	50	100.00
V2	burst_write	kmac_burst_write	14.693m	149.690ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.592m	486.402ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.197m	832.432ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.738m	908.574ms	50	50	100.00
		kmac_test_vectors_sha3_512	16.923m	98.648ms	50	50	100.00
		kmac_test_vectors_shake_128	1.519h	526.555ms	50	50	100.00
		kmac_test_vectors_shake_256	1.400h	1.444s	50	50	100.00
		kmac_test_vectors_kmac	6.030s	2.229ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.370s	491.907us	50	50	100.00
V2	sideload	kmac_sideload	6.772m	73.301ms	50	50	100.00
V2	app	kmac_app	6.174m	74.224ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.793m	17.347ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.111m	22.427ms	48	50	96.00
V2	error	kmac_error	7.559m	46.594ms	50	50	100.00
V2	key_error	kmac_key_error	10.950s	2.013ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.890s	14.233ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	36.000s	3.488ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.293m	32.749ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.810s	3.464ms	50	50	100.00
V2	stress_all	kmac_stress_all	47.017m	406.292ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.900s	17.215us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	118.938us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.250s	120.388us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.250s	120.388us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	18.786us	5	5	100.00
		kmac_csr_rw	1.200s	34.492us	20	20	100.00
		kmac_csr_aliasing	9.740s	546.416us	5	5	100.00
		kmac_same_csr_outstanding	2.810s	97.360us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	18.786us	5	5	100.00
		kmac_csr_rw	1.200s	34.492us	20	20	100.00
		kmac_csr_aliasing	9.740s	546.416us	5	5	100.00
		kmac_same_csr_outstanding	2.810s	97.360us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.430s	104.948us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.430s	104.948us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.430s	104.948us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.430s	104.948us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.070s	536.512us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.337m	12.105ms	5	5	100.00
		kmac_tl_intg_err	5.360s	324.667us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.360s	324.667us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.810s	3.464ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.165m	16.069ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.772m	73.301ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.430s	104.948us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.337m	12.105ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.337m	12.105ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.337m	12.105ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.165m	16.069ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.810s	3.464ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.337m	12.105ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.434m	36.581ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.165m	16.069ms	50	50	100.00
V2S		TOTAL			72	75	96.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.224m	159.763ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			1253	1290	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.43	95.88	92.30	100.00	69.42	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test kmac_stress_all_with_rand_reset has 25 failures.
  - 0.kmac_stress_all_with_rand_reset.100560657254680572508722527395258390202296876894357722592067218089888805949100
    Line 752, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 58193726022 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 58193726022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.101571162258399093534233770014596631546557975591034124154640708066159301911266
    Line 1143, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10783088391 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10783088391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 12.kmac_stress_all_with_rand_reset.114272150450719965026285230657618694942984443564364416919862385973972855435154
    Line 2833, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37530442318 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 37530442318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.kmac_stress_all_with_rand_reset.104586872676396919864295167322269847293786687024883969984106557308643214593374
    Line 297, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 282097052 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 282097052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.
  - 9.kmac_shadow_reg_errors_with_csr_rw.70283194651844466258045121770683976478233644141866847819111358383817704198211
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 140470520 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 140470520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_shadow_reg_errors_with_csr_rw.4445257318568451749981199681921769985164046390591723558064428709919372943571
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  19161446 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  19161446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_entropy_refresh has 2 failures.

8.kmac_entropy_refresh.93967799877887896446626574820374665395722512731005030447987791462707029093652
Line 481, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 18042845329 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (179 [0xb3] vs 64 [0x40]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 18042845329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.kmac_entropy_refresh.58400194283502148717559195026658173105593731189949359811737757820890622886720
Line 357, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6481992957 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (128 [0x80] vs 97 [0x61]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6481992957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 32.kmac_burst_write.103375567424041046709948218364018968990309389575752801377074604859832328211851
    Line 692, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```