KMAC/UNMASKED Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.279m	4.104ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	127.636us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.350s	446.364us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.680s	997.156us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	12.350s	6.476ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	131.563us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.350s	446.364us	20	20	100.00
		kmac_csr_aliasing	12.350s	6.476ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	12.142us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	128.943us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.414m	266.453ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.793m	103.716ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.484m	422.565ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.284m	1.205s	50	50	100.00
		kmac_test_vectors_sha3_384	27.679m	996.305ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.002m	136.638ms	50	50	100.00
		kmac_test_vectors_shake_128	1.715h	1.970s	50	50	100.00
		kmac_test_vectors_shake_256	1.482h	2.666s	50	50	100.00
		kmac_test_vectors_kmac	6.180s	1.709ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.740s	3.147ms	50	50	100.00
V2	sideload	kmac_sideload	7.486m	178.636ms	50	50	100.00
V2	app	kmac_app	5.707m	19.569ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.670m	72.052ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.747m	10.573ms	50	50	100.00
V2	error	kmac_error	7.690m	162.062ms	50	50	100.00
V2	key_error	kmac_key_error	13.440s	22.649ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.020s	5.183ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.370s	8.120ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.120m	8.611ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	48.730s	2.405ms	50	50	100.00
V2	stress_all	kmac_stress_all	43.963m	89.664ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.840s	27.746us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	28.729us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.310s	121.212us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.310s	121.212us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	127.636us	5	5	100.00
		kmac_csr_rw	1.350s	446.364us	20	20	100.00
		kmac_csr_aliasing	12.350s	6.476ms	5	5	100.00
		kmac_same_csr_outstanding	2.880s	503.497us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	127.636us	5	5	100.00
		kmac_csr_rw	1.350s	446.364us	20	20	100.00
		kmac_csr_aliasing	12.350s	6.476ms	5	5	100.00
		kmac_same_csr_outstanding	2.880s	503.497us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.540s	102.529us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.540s	102.529us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.540s	102.529us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.540s	102.529us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.880s	186.035us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.134m	43.492ms	5	5	100.00
		kmac_tl_intg_err	5.470s	3.473ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.470s	3.473ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	48.730s	2.405ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.279m	4.104ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.486m	178.636ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.540s	102.529us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.134m	43.492ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.134m	43.492ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.134m	43.492ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.279m	4.104ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	48.730s	2.405ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.134m	43.492ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.031m	8.270ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.279m	4.104ms	50	50	100.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	35.157m	483.969ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			1247	1290	96.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.33	95.88	92.34	100.00	68.60	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test kmac_stress_all_with_rand_reset has 31 failures.
  - 0.kmac_stress_all_with_rand_reset.24698219035604435886309054928931616756652503501552904984518866357714655790935
    Line 716, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18345078128 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18345078128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.52540011916897721851087490458787974419416706305336423622780412123108594160925
    Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 450248835 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 450248835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status

has 6 failures:

Test kmac_shadow_reg_errors has 3 failures.

0.kmac_shadow_reg_errors.21157580650225633822923833046130918960566609946475270340226949984319344638795
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  23620206 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  23620206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors.39637288180436977034331058600457051385470634013842541163067379202029010989974
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  20540885 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  20540885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

1.kmac_shadow_reg_errors_with_csr_rw.101881030644786833287286962324239386055341129369805155991037731833150438022476
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 211286177 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 211286177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.58430418557984861995918294076817516664423231708171783716700003962664216259968
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  32767067 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  32767067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 5.kmac_stress_all_with_rand_reset.81073950178330485663021326532262399980316322011109360233950005938912036901458
    Line 1982, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 186157267339 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 186157267339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.kmac_stress_all_with_rand_reset.41042547777942061200051859019330000507578965433720120530232949468868093354338
    Line 380, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36230868363 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 36230868363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 3 failures:

Test kmac_app has 2 failures.

7.kmac_app.32305790115329029051463317201384888697182030018492433738543423954102982144140
Line 545, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app/latest/run.log

  UVM_FATAL @ 11482638799 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (17 [0x11] vs 141 [0x8d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11482638799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.kmac_app.8100150389828525353329293426437714953178834976167455028111748370726871569960
Line 441, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_app/latest/run.log

  UVM_FATAL @ 8742922002 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (104 [0x68] vs 99 [0x63]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8742922002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

13.kmac_stress_all.20939914193658499158091797122026448728544565557544629691007620986813944455145
Line 485, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest/run.log

  UVM_FATAL @ 3700841164 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (195 [0xc3] vs 235 [0xeb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3700841164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---