KMAC/UNMASKED Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.087m	9.723ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	175.088us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	56.151us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.250s	1.540ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.810s	1.376ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.560s	40.775us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	56.151us	20	20	100.00
		kmac_csr_aliasing	5.810s	1.376ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	40.806us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	76.561us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.667m	341.668ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.444m	124.716ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.757m	396.022ms	50	50	100.00
		kmac_test_vectors_sha3_256	37.501m	1.506s	50	50	100.00
		kmac_test_vectors_sha3_384	26.800m	1.010s	50	50	100.00
		kmac_test_vectors_sha3_512	17.850m	50.714ms	50	50	100.00
		kmac_test_vectors_shake_128	1.673h	4.195s	50	50	100.00
		kmac_test_vectors_shake_256	1.554h	4.344s	50	50	100.00
		kmac_test_vectors_kmac	5.880s	2.418ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.410s	1.012ms	50	50	100.00
V2	sideload	kmac_sideload	7.005m	78.728ms	50	50	100.00
V2	app	kmac_app	5.737m	19.200ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.759m	23.727ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.787m	77.227ms	50	50	100.00
V2	error	kmac_error	6.971m	38.034ms	50	50	100.00
V2	key_error	kmac_key_error	11.710s	4.348ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	37.850s	2.989ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.760s	4.245ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.180m	59.232ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.580s	1.932ms	50	50	100.00
V2	stress_all	kmac_stress_all	32.142m	95.536ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.820s	47.923us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	31.772us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.610s	152.162us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.610s	152.162us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	175.088us	5	5	100.00
		kmac_csr_rw	1.200s	56.151us	20	20	100.00
		kmac_csr_aliasing	5.810s	1.376ms	5	5	100.00
		kmac_same_csr_outstanding	2.560s	513.589us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	175.088us	5	5	100.00
		kmac_csr_rw	1.200s	56.151us	20	20	100.00
		kmac_csr_aliasing	5.810s	1.376ms	5	5	100.00
		kmac_same_csr_outstanding	2.560s	513.589us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	52.154us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	52.154us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	52.154us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	52.154us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.980s	502.580us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.139m	37.213ms	5	5	100.00
		kmac_tl_intg_err	5.570s	412.647us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.570s	412.647us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.580s	1.932ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.087m	9.723ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.005m	78.728ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	52.154us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.139m	37.213ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.139m	37.213ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.139m	37.213ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.087m	9.723ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.580s	1.932ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.139m	37.213ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.647m	60.873ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.087m	9.723ms	50	50	100.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	56.753m	95.412ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			1245	1290	96.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.29	95.91	92.41	100.00	67.77	94.19	99.00	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test kmac_stress_all_with_rand_reset has 36 failures.
  - 0.kmac_stress_all_with_rand_reset.97109397878375324618399326406242287739616146553988474070196977496401746418691
    Line 2609, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 199201380455 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 199201380455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.56934051134469409718885122032483851302728083231373128407737105449788294085460
    Line 312, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3219617909 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3219617909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_mubi has 1 failures.

2.kmac_mubi.36790905433239971391979379070678308413537797334228316102643193005466747213658
Line 405, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_mubi/latest/run.log

  UVM_FATAL @ 2383232048 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (105 [0x69] vs 152 [0x98]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2383232048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

43.kmac_app.58555090222348788832787602662714827344993825028070297501085970341189618701753
Line 373, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_app/latest/run.log

  UVM_FATAL @ 670828571 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (173 [0xad] vs 221 [0xdd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 670828571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.kmac_app.93884630995457541013137593095037748181094042410282269464792440522224534557616
Line 315, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_app/latest/run.log

  UVM_FATAL @ 2435362005 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (53 [0x35] vs 26 [0x1a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2435362005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:

Test kmac_shadow_reg_errors has 1 failures.

4.kmac_shadow_reg_errors.90523839791479726323281814111857399935867401722322898761645887081266015045908
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   5646602 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   5646602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

10.kmac_shadow_reg_errors_with_csr_rw.35658834023199436853482592775495697641930296764144567083683836860501772719023
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  15405217 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  15405217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.kmac_shadow_reg_errors_with_csr_rw.49532472970737001811299219063423345253476758132621255726342179020723334115178
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  43585482 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  43585482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 6.kmac_stress_all_with_rand_reset.107901608382892420586605644691384967988944887089972211924498488830465983506022
    Line 683, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 69996102999 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 69996102999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.kmac_stress_all_with_rand_reset.12373275685794097635107569015439256537045362633702105960108934565858722783727
    Line 653, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37738061307 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 37738061307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 12.kmac_burst_write.108669440107428995871988907540799811627791538918787071712975643616175932105557
    Line 639, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```