KMAC/UNMASKED Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.284m	17.285ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	136.379us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	307.098us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.130s	1.017ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.060s	919.718us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.500s	91.307us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	307.098us	20	20	100.00
		kmac_csr_aliasing	9.060s	919.718us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	19.533us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	39.517us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.825m	854.440ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.171m	24.335ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.981m	396.728ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.473m	376.106ms	50	50	100.00
		kmac_test_vectors_sha3_384	29.586m	1.184s	50	50	100.00
		kmac_test_vectors_sha3_512	20.721m	830.335ms	50	50	100.00
		kmac_test_vectors_shake_128	1.539h	499.969ms	50	50	100.00
		kmac_test_vectors_shake_256	1.401h	2.180s	50	50	100.00
		kmac_test_vectors_kmac	5.330s	479.362us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.320s	705.127us	50	50	100.00
V2	sideload	kmac_sideload	7.517m	90.403ms	50	50	100.00
V2	app	kmac_app	5.338m	136.697ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.425m	42.257ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.249m	19.604ms	48	50	96.00
V2	error	kmac_error	7.497m	61.758ms	50	50	100.00
V2	key_error	kmac_key_error	10.000s	7.811ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.550s	31.793ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.230s	8.294ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	53.110s	22.934ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.160s	1.975ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.012m	187.195ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	36.763us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	210.571us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.030s	904.909us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.030s	904.909us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	136.379us	5	5	100.00
		kmac_csr_rw	1.210s	307.098us	20	20	100.00
		kmac_csr_aliasing	9.060s	919.718us	5	5	100.00
		kmac_same_csr_outstanding	2.630s	240.899us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	136.379us	5	5	100.00
		kmac_csr_rw	1.210s	307.098us	20	20	100.00
		kmac_csr_aliasing	9.060s	919.718us	5	5	100.00
		kmac_same_csr_outstanding	2.630s	240.899us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.310s	606.734us	16	20	80.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.310s	606.734us	16	20	80.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.310s	606.734us	16	20	80.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.310s	606.734us	16	20	80.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.880s	242.426us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	48.880s	3.189ms	5	5	100.00
		kmac_tl_intg_err	5.320s	513.157us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.320s	513.157us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.160s	1.975ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.284m	17.285ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.517m	90.403ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.310s	606.734us	16	20	80.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	48.880s	3.189ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	48.880s	3.189ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	48.880s	3.189ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.284m	17.285ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.160s	1.975ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	48.880s	3.189ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.498m	68.836ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.284m	17.285ms	50	50	100.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	36.386m	46.982ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			1238	1290	95.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.10	95.88	92.34	100.00	66.94	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test kmac_stress_all_with_rand_reset has 35 failures.
  - 2.kmac_stress_all_with_rand_reset.63778116833891545962663131547805588584075157958651607026797885887630290865460
    Line 514, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3004490614 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3004490614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.78941385817391559615149524896062810055495701190494291850022414302608462243879
    Line 505, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33874147807 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33874147807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 1.kmac_stress_all_with_rand_reset.51667776917506069080475301831218742607978696887321735799715347621256639095424
    Line 443, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10985678989 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 10985678989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.kmac_stress_all_with_rand_reset.7317591785829330339751818388828455049515642756868670396481233519408825265645
    Line 2073, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 75899710215 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 75899710215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:

Test kmac_shadow_reg_errors has 4 failures.

1.kmac_shadow_reg_errors.111191568113122828929399287032425770157806229466444188197468053249633720424731
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   6909897 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   6909897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors.103869161857724179887827001238987244951828994081080290763740220119248981696391
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  21260099 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  21260099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app has 1 failures.

11.kmac_app.92973751382099012490229208994455525952347959588977965921343230456897668578252
Line 501, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_app/latest/run.log

  UVM_FATAL @ 3352727229 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (245 [0xf5] vs 156 [0x9c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3352727229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

41.kmac_stress_all.74947120327944262152064526848768895598273885487311843255322337403858637881373
Line 1209, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest/run.log

  UVM_FATAL @ 92713749886 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (120 [0x78] vs 50 [0x32]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 92713749886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

46.kmac_entropy_refresh.44707341129905075586412409035531634317424792065779259790624153671116754250704
Line 537, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 37118568089 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (152 [0x98] vs 102 [0x66]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 37118568089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 1 failures.
  - 11.kmac_burst_write.77237049092232938007261621791651691763233327677035818857496074817711189281786
    Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 40.kmac_entropy_refresh.105156000808679519068943748861063593818539328201461670925594220857727085386386
    Line 877, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 7.kmac_key_error.2949142299190273523395920672283035188338820932295037718189283372623862491721
    Line 267, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 3613678613 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 3613678613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```