KMAC/UNMASKED Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.197m	5.120ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	127.484us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	50.064us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.820s	1.245ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.930s	1.427ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.650s	137.519us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	50.064us	20	20	100.00
		kmac_csr_aliasing	9.930s	1.427ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	15.953us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	38.177us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.470m	279.706ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.739m	131.190ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	40.812m	1.397s	50	50	100.00
		kmac_test_vectors_sha3_256	32.702m	437.108ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.342m	691.837ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.311m	348.199ms	50	50	100.00
		kmac_test_vectors_shake_128	1.575h	2.312s	50	50	100.00
		kmac_test_vectors_shake_256	1.466h	3.652s	50	50	100.00
		kmac_test_vectors_kmac	5.430s	2.114ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.430s	940.533us	50	50	100.00
V2	sideload	kmac_sideload	7.161m	21.288ms	50	50	100.00
V2	app	kmac_app	5.533m	58.149ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.325m	40.908ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.395m	42.408ms	49	50	98.00
V2	error	kmac_error	7.437m	32.596ms	50	50	100.00
V2	key_error	kmac_key_error	9.700s	1.906ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.960s	5.832ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.610s	4.848ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.036m	22.510ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	19.600s	4.142ms	50	50	100.00
V2	stress_all	kmac_stress_all	25.486m	66.766ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.840s	27.736us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	41.251us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.120s	828.896us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.120s	828.896us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	127.484us	5	5	100.00
		kmac_csr_rw	1.180s	50.064us	20	20	100.00
		kmac_csr_aliasing	9.930s	1.427ms	5	5	100.00
		kmac_same_csr_outstanding	2.590s	233.513us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	127.484us	5	5	100.00
		kmac_csr_rw	1.180s	50.064us	20	20	100.00
		kmac_csr_aliasing	9.930s	1.427ms	5	5	100.00
		kmac_same_csr_outstanding	2.590s	233.513us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.330s	42.857us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.330s	42.857us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.330s	42.857us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.330s	42.857us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.910s	95.449us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	53.170s	5.143ms	5	5	100.00
		kmac_tl_intg_err	5.880s	3.194ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.880s	3.194ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	19.600s	4.142ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.197m	5.120ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.161m	21.288ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.330s	42.857us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	53.170s	5.143ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	53.170s	5.143ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	53.170s	5.143ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.197m	5.120ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	19.600s	4.142ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	53.170s	5.143ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.017m	39.275ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.197m	5.120ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	38.505m	363.656ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			1241	1290	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.33	95.88	92.30	100.00	68.60	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test kmac_stress_all_with_rand_reset has 34 failures.
  - 3.kmac_stress_all_with_rand_reset.61939514301015776862788299031087548583602011700211945331875796203113592552377
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 381897800 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 381897800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.74276794492252207777497577885931775420727488781683091651669595415468543903379
    Line 1344, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 160313033879 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 160313033879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 2.kmac_stress_all_with_rand_reset.25428824992112692603961030470193936777464041183250277031902025138738465178838
    Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  58240536 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @  58240536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.kmac_stress_all_with_rand_reset.85521169991135852588090277534306863477020903219684435051694526240153624231565
    Line 1292, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34679724614 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 34679724614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

10.kmac_shadow_reg_errors_with_csr_rw.27888577356386375264616592534546964018201566059090339019237766325534552882998
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  38410255 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  38410255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.kmac_shadow_reg_errors_with_csr_rw.27785856217050883636348289809310525189214557578288541087462742567031476260589
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  15359432 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  15359432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors has 1 failures.

13.kmac_shadow_reg_errors.1622334583883712144853777744999243074416636776512070434963892888710772094014
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  34357625 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  34357625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 1 failures.
  - 20.kmac_burst_write.2792134961085655504797202697676272592200590673774303924390134217652655393083
    Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 40.kmac_entropy_refresh.89928402340130025213962101315492138047404821307517003703901767979411291277242
    Line 796, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 6.kmac_shadow_reg_errors_with_csr_rw.98541963174111019535135791847281673772181956568433246202177760745308431773422
    Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 123498047 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1180564227 [0x465dfb03] vs 0 [0x0]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
  UVM_INFO @ 123498047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 7.kmac_key_error.70135870308992590079740102633879899066832971679393129038516118735332716655018
    Line 273, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 2417684009 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 2417684009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 8.kmac_app_with_partial_data.94256729790137749862027040261616537376767066563604276007859233083944995628313
    Line 567, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 1861859887 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (177 [0xb1] vs 119 [0x77]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1861859887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```