KMAC/UNMASKED Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.100m	14.094ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	58.065us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.170s	35.064us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.490s	994.567us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.850s	561.555us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.550s	78.775us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.170s	35.064us	20	20	100.00
		kmac_csr_aliasing	7.850s	561.555us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	22.507us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	81.955us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	46.329m	135.264ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.982m	64.696ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.018m	1.976s	50	50	100.00
		kmac_test_vectors_sha3_256	32.441m	752.103ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.043m	294.437ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.440m	244.512ms	50	50	100.00
		kmac_test_vectors_shake_128	1.613h	3.490s	50	50	100.00
		kmac_test_vectors_shake_256	1.305h	1.265s	50	50	100.00
		kmac_test_vectors_kmac	5.610s	1.405ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.040s	2.679ms	50	50	100.00
V2	sideload	kmac_sideload	7.010m	32.257ms	50	50	100.00
V2	app	kmac_app	5.538m	13.952ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.280m	74.493ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.377m	111.146ms	49	50	98.00
V2	error	kmac_error	7.087m	14.815ms	50	50	100.00
V2	key_error	kmac_key_error	10.360s	2.049ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.520s	4.281ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.760s	4.392ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.226m	75.904ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.600s	3.073ms	50	50	100.00
V2	stress_all	kmac_stress_all	35.998m	78.337ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.850s	52.974us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	226.502us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.500s	296.379us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.500s	296.379us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	58.065us	5	5	100.00
		kmac_csr_rw	1.170s	35.064us	20	20	100.00
		kmac_csr_aliasing	7.850s	561.555us	5	5	100.00
		kmac_same_csr_outstanding	2.400s	102.445us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	58.065us	5	5	100.00
		kmac_csr_rw	1.170s	35.064us	20	20	100.00
		kmac_csr_aliasing	7.850s	561.555us	5	5	100.00
		kmac_same_csr_outstanding	2.400s	102.445us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.490s	97.375us	16	20	80.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.490s	97.375us	16	20	80.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.490s	97.375us	16	20	80.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.490s	97.375us	16	20	80.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.950s	489.744us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	1.296m	35.394ms	5	5	100.00
		kmac_tl_intg_err	4.930s	249.116us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.930s	249.116us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.600s	3.073ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.100m	14.094ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.010m	32.257ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.490s	97.375us	16	20	80.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.296m	35.394ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.296m	35.394ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.296m	35.394ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.100m	14.094ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.600s	3.073ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.296m	35.394ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.905m	43.482ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.100m	14.094ms	50	50	100.00
V2S		TOTAL			66	75	88.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.715m	149.617ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			1236	1290	95.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.11	95.88	92.27	100.00	66.94	94.11	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test kmac_stress_all_with_rand_reset has 33 failures.
  - 2.kmac_stress_all_with_rand_reset.87193293107495936127631711317726430753643219773038976174103541966503305197558
    Line 516, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31507767877 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31507767877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.12025689516641549600098789000996319719833925543257501173947331350752213909994
    Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 203549296804 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 203549296804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 9 failures:

Test kmac_shadow_reg_errors has 4 failures.

1.kmac_shadow_reg_errors.101950775467258461608585992158264976428923482972998636251080929873099424900064
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  72084460 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  72084460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors.92830331468188600011374357418810394967446043635123026992490348306104612845748
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  97816003 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  97816003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

3.kmac_shadow_reg_errors_with_csr_rw.36080746328784790870230347086488707618957673791962810144929815851946210185620
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 143824961 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 143824961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_shadow_reg_errors_with_csr_rw.104071729342337919260986159703820205777205370061636467798825521841772309997021
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 106640810 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 106640810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 21.kmac_stress_all_with_rand_reset.105560511780714716262985409470339473793847416225351124522178534273056977223559
    Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 133491661 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 133491661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.kmac_stress_all_with_rand_reset.99632865621657332865425709344828328092507731662414586739168670312051967628816
    Line 670, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17804676168 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 17804676168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 1 failures.

4.kmac_app.58226242776923234021117978734189429584337204021834320494636517359860420176962
Line 357, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_app/latest/run.log

  UVM_FATAL @ 1553763884 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (163 [0xa3] vs 94 [0x5e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1553763884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

13.kmac_stress_all_with_rand_reset.33195839709004982795521487221020252003569335521262528210763187718853663497913
Line 2614, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 65538216567 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (237 [0xed] vs 112 [0x70]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 65538216567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

32.kmac_stress_all.54166850293993497544501583421930285269391326727089039122786014772456140411824
Line 509, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest/run.log

  UVM_FATAL @ 6501506512 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (9 [0x9] vs 20 [0x14]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6501506512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

42.kmac_entropy_refresh.75819747196530163199693658839620161259783257973161851207408358754077591326279
Line 631, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 4230236174 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (47 [0x2f] vs 102 [0x66]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4230236174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 3.kmac_burst_write.36516483355237538157337658001142524552390974737309904589362287222177875212624
    Line 722, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 6.kmac_key_error.14842762485084974988717879551992923289724766197150374474166214507753259889384
    Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1506721200 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1506721200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```