KMAC/UNMASKED Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.162m	46.284ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.030s	105.309us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.160s	107.787us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.440s	5.717ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.140s	393.324us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	81.758us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.160s	107.787us	20	20	100.00
		kmac_csr_aliasing	9.140s	393.324us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	18.552us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	120.060us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.328m	1.103s	50	50	100.00
V2	burst_write	kmac_burst_write	14.070m	25.366ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.398m	409.162ms	50	50	100.00
		kmac_test_vectors_sha3_256	37.450m	1.013s	50	50	100.00
		kmac_test_vectors_sha3_384	30.898m	1.388s	50	50	100.00
		kmac_test_vectors_sha3_512	17.878m	347.848ms	50	50	100.00
		kmac_test_vectors_shake_128	1.725h	4.436s	50	50	100.00
		kmac_test_vectors_shake_256	1.371h	4.365s	50	50	100.00
		kmac_test_vectors_kmac	5.430s	544.132us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.550s	521.239us	50	50	100.00
V2	sideload	kmac_sideload	7.893m	21.012ms	50	50	100.00
V2	app	kmac_app	6.054m	17.983ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.926m	63.920ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.600m	132.520ms	50	50	100.00
V2	error	kmac_error	7.135m	29.300ms	50	50	100.00
V2	key_error	kmac_key_error	8.790s	8.913ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.880s	15.451ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.540s	4.050ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	50.700s	4.760ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.130s	2.037ms	50	50	100.00
V2	stress_all	kmac_stress_all	28.706m	298.137ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	16.464us	50	50	100.00
V2	alert_test	kmac_alert_test	0.850s	48.391us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.310s	91.187us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.310s	91.187us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.030s	105.309us	5	5	100.00
		kmac_csr_rw	1.160s	107.787us	20	20	100.00
		kmac_csr_aliasing	9.140s	393.324us	5	5	100.00
		kmac_same_csr_outstanding	2.540s	222.096us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.030s	105.309us	5	5	100.00
		kmac_csr_rw	1.160s	107.787us	20	20	100.00
		kmac_csr_aliasing	9.140s	393.324us	5	5	100.00
		kmac_same_csr_outstanding	2.540s	222.096us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	175.461us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	175.461us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	175.461us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	175.461us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.010s	959.153us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.256m	18.583ms	5	5	100.00
		kmac_tl_intg_err	5.770s	899.847us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.770s	899.847us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.130s	2.037ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.162m	46.284ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.893m	21.012ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	175.461us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.256m	18.583ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.256m	18.583ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.256m	18.583ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.162m	46.284ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.130s	2.037ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.256m	18.583ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.715m	25.431ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.162m	46.284ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	29.008m	1.829s	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1235	1250	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.12	95.91	92.38	100.00	66.94	94.19	99.00	96.43

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:

  • Test kmac_stress_all_with_rand_reset has 7 failures.

    • 0.kmac_stress_all_with_rand_reset.91939838063754411445833598241457536252835890820831328477182999209797789007471
      Line 488, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10275246756 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10275246756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.8941046293036225025895308070834920778975600438840363006913798354868485345689
      Line 2880, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 85589262592 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 85589262592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test kmac_app_with_partial_data has 1 failures.

    • 1.kmac_app_with_partial_data.33714972555668435273078433341593007959585233351424696252638219043148513193314
      Line 686, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_app has 1 failures.

    • 37.kmac_app.99464415430636045819568343234862684493813289508339688777515235319576185874642
      Line 900, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_app/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 5.kmac_stress_all_with_rand_reset.26306429872230824116208094827695675883325274363123196182593455708459134242853
      Line 1006, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 52852191545 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 52852191545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.kmac_stress_all_with_rand_reset.9475635721258210143069054735444571744757170678787598233631873754597868584463
      Line 1074, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 62989385252 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 62989385252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 2 failures:

  • Test kmac_shadow_reg_errors has 1 failures.

    • 5.kmac_shadow_reg_errors.14939878753354284409177282697900959804037019573194580437988182329130343887116
      Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest/run.log

        UVM_ERROR @  11850724 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
        UVM_INFO @  11850724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 12.kmac_shadow_reg_errors_with_csr_rw.35814554867137869637928761352801309071644511289443192435778997457691512234173
      Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @ 223031104 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
        UVM_INFO @ 223031104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1339) [scoreboard] Check failed digest_share*.size() == output_len_bytes (* [*] vs * [*]) Calculated output length(32) doesn't match actual output length(48)! has 1 failures:

  • Test kmac_app has 1 failures.

    • 30.kmac_app.96707126613009616308007457768990503479536119055830567426646534127001120471500
      Line 323, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_app/latest/run.log

        UVM_FATAL @ 2084466793 ps: (kmac_scoreboard.sv:1339) [uvm_test_top.env.scoreboard] Check failed digest_share0.size() == output_len_bytes (48 [0x30] vs 32 [0x20]) Calculated output length(32) doesn't match actual output length(48)!
        UVM_INFO @ 2084466793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:

  • Test kmac_app has 1 failures.

    • 42.kmac_app.45581652186588829207641134981792953033997474536601290416826314549626481864967
      Line 845, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_app/latest/run.log

        UVM_FATAL @ 33401053822 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (32 [0x20] vs 34 [0x22]) Mismatch between unmasked_digest[1] and dpi_digest[1]
        UVM_INFO @ 33401053822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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