KMAC/UNMASKED Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.131m	4.144ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.080s	137.653us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.160s	414.333us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.370s	1.007ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.610s	1.004ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.870s	1.723ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.160s	414.333us	20	20	100.00
		kmac_csr_aliasing	5.610s	1.004ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	20.267us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	69.271us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	44.280m	1.256s	50	50	100.00
V2	burst_write	kmac_burst_write	15.143m	146.848ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.072m	776.841ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.059m	678.272ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.704m	593.950ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.131m	246.051ms	50	50	100.00
		kmac_test_vectors_shake_128	1.617h	3.710s	50	50	100.00
		kmac_test_vectors_shake_256	1.426h	2.175s	50	50	100.00
		kmac_test_vectors_kmac	5.930s	2.225ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.560s	254.958us	50	50	100.00
V2	sideload	kmac_sideload	9.607m	439.554ms	50	50	100.00
V2	app	kmac_app	5.604m	62.606ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.017m	16.046ms	8	10	80.00
V2	entropy_refresh	kmac_entropy_refresh	5.762m	76.647ms	49	50	98.00
V2	error	kmac_error	7.361m	169.929ms	50	50	100.00
V2	key_error	kmac_key_error	10.280s	9.453ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.220s	6.653ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	48.920s	11.287ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.161m	7.416ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	40.910s	1.027ms	50	50	100.00
V2	stress_all	kmac_stress_all	55.095m	330.897ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.830s	49.706us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	27.785us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.300s	132.086us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.300s	132.086us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.080s	137.653us	5	5	100.00
		kmac_csr_rw	1.160s	414.333us	20	20	100.00
		kmac_csr_aliasing	5.610s	1.004ms	5	5	100.00
		kmac_same_csr_outstanding	2.750s	607.602us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.080s	137.653us	5	5	100.00
		kmac_csr_rw	1.160s	414.333us	20	20	100.00
		kmac_csr_aliasing	5.610s	1.004ms	5	5	100.00
		kmac_same_csr_outstanding	2.750s	607.602us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.420s	182.347us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.420s	182.347us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.420s	182.347us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.420s	182.347us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.780s	182.863us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.242m	5.892ms	5	5	100.00
		kmac_tl_intg_err	5.470s	1.894ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.470s	1.894ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	40.910s	1.027ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.131m	4.144ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.607m	439.554ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.420s	182.347us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.242m	5.892ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.242m	5.892ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.242m	5.892ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.131m	4.144ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	40.910s	1.027ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.242m	5.892ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.980m	44.445ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.131m	4.144ms	50	50	100.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	22.200m	88.236ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1234	1250	98.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.82	95.89	92.34	100.00	65.29	94.11	98.84	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.90336212236299118208860947352486960691348696996174462338099503695877789116323
    Line 936, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16400760201 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16400760201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.29084007228255914057237180674187599500959035036030505224028851384456825772525
    Line 518, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13884471829 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13884471829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

0.kmac_shadow_reg_errors_with_csr_rw.62532935079112747495774629999413926775601868853456035038642080199825713111863
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  57477989 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  57477989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.kmac_shadow_reg_errors_with_csr_rw.100569029299839762651503145842505644777885326498965467690074707653725774428252
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  25777308 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  25777308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 2 failures.

11.kmac_shadow_reg_errors.6430893832644790751458245283350576493223966359098739182259626119844385043090
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   3630440 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   3630440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.kmac_shadow_reg_errors.107109545584322380017106732681261458772070622024018987636224917167944757241236
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   7321897 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   7321897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app_with_partial_data has 1 failures.

2.kmac_app_with_partial_data.46875830273111819267799596669307128695891041019173091607577346096280420740219
Line 701, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 17989667594 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (233 [0xe9] vs 149 [0x95]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17989667594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

35.kmac_stress_all.48359051353856589647938525140796683512322602150665948110757675701965682470249
Line 2013, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest/run.log

  UVM_FATAL @ 430091649301 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (139 [0x8b] vs 116 [0x74]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 430091649301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

36.kmac_entropy_refresh.38359598707511344329896471186955040777588021593075446673059727315407422549131
Line 1097, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 32787456329 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (155 [0x9b] vs 21 [0x15]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 32787456329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 6.kmac_app_with_partial_data.82771632312414954505201122220323478261516482280702282575520965778043731238760
    Line 666, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 7.kmac_stress_all_with_rand_reset.95052688724145062740903458122107689965406226887344069459306247977772835057166
    Line 502, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7035883357 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 7035883357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```