KMAC/UNMASKED Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.159m	20.934ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	40.831us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	105.762us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.350s	1.446ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.350s	531.543us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.650s	263.141us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	105.762us	20	20	100.00
		kmac_csr_aliasing	10.350s	531.543us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	17.996us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	127.937us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.943m	1.011s	50	50	100.00
V2	burst_write	kmac_burst_write	13.633m	101.632ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.293m	1.079s	50	50	100.00
		kmac_test_vectors_sha3_256	32.700m	205.785ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.877m	290.120ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.094m	183.240ms	50	50	100.00
		kmac_test_vectors_shake_128	1.522h	257.338ms	50	50	100.00
		kmac_test_vectors_shake_256	1.317h	2.677s	50	50	100.00
		kmac_test_vectors_kmac	5.310s	254.086us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.600s	1.125ms	50	50	100.00
V2	sideload	kmac_sideload	7.214m	18.973ms	50	50	100.00
V2	app	kmac_app	5.406m	17.349ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.434m	23.311ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.425m	200.000ms	47	50	94.00
V2	error	kmac_error	8.018m	85.609ms	50	50	100.00
V2	key_error	kmac_key_error	9.630s	1.803ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.280s	1.929ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	32.240s	468.351us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.069m	82.998ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.380s	663.253us	50	50	100.00
V2	stress_all	kmac_stress_all	36.503m	209.406ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.890s	151.632us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	48.185us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.330s	446.507us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.330s	446.507us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	40.831us	5	5	100.00
		kmac_csr_rw	1.230s	105.762us	20	20	100.00
		kmac_csr_aliasing	10.350s	531.543us	5	5	100.00
		kmac_same_csr_outstanding	2.760s	128.918us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	40.831us	5	5	100.00
		kmac_csr_rw	1.230s	105.762us	20	20	100.00
		kmac_csr_aliasing	10.350s	531.543us	5	5	100.00
		kmac_same_csr_outstanding	2.760s	128.918us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.350s	59.217us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.350s	59.217us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.350s	59.217us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.350s	59.217us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.130s	522.582us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	58.750s	12.232ms	5	5	100.00
		kmac_tl_intg_err	5.020s	1.149ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.020s	1.149ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.380s	663.253us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.159m	20.934ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.214m	18.973ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.350s	59.217us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	58.750s	12.232ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	58.750s	12.232ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	58.750s	12.232ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.159m	20.934ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.380s	663.253us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	58.750s	12.232ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.380m	68.645ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.159m	20.934ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.707m	115.811ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1234	1250	98.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.19	95.89	92.27	100.00	67.77	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.25645813995594291716987470007369622977401944633322329073468522562083394225963
    Line 569, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31824464176 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31824464176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.32720545492311386133973139543146277405565570889755280602186558744914021763496
    Line 305, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2853412975 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2853412975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app_with_partial_data has 1 failures.

2.kmac_app_with_partial_data.9778701718486633305558816072652827914412689493529765335642610264931775668568
Line 523, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 6306358291 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (149 [0x95] vs 0 [0x0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6306358291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

3.kmac_mubi.48512642998239578164248156904263392566781434619069586916021860609967539198902
Line 1111, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_mubi/latest/run.log

  UVM_FATAL @ 11674448905 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (208 [0xd0] vs 164 [0xa4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11674448905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

7.kmac_app.70594456294553273910661694447734628526722190251715892240602948342446750731302
Line 321, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app/latest/run.log

  UVM_FATAL @ 5491975380 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (135 [0x87] vs 105 [0x69]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5491975380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

20.kmac_entropy_refresh.33906046486706581830614332468627277273214947434311709115507062460601908861651
Line 541, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 19946276037 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (63 [0x3f] vs 221 [0xdd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 19946276037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.kmac_entropy_refresh.90058085369530897086453088047995185651467047534673005207420261764223662060782
Line 485, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 10022982485 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (142 [0x8e] vs 14 [0xe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10022982485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 12.kmac_entropy_refresh.8191973989862677498676847324099171389606789271688250116267666371990396508284
    Line 998, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 2 failures.
  - 38.kmac_burst_write.21582827659191540382132862589727201105547362909816513469084701821201251800194
    Line 897, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.kmac_burst_write.83566877972309231972572587283717548871044993417252590219920456791814761091096
    Line 591, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```