KMAC/UNMASKED Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.080m	36.172ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	287.369us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	27.622us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.900s	4.030ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.160s	527.953us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.720s	1.213ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	27.622us	20	20	100.00
		kmac_csr_aliasing	10.160s	527.953us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	10.326us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.530s	39.695us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.194m	545.759ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.834m	141.263ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.077m	102.743ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.041m	466.768ms	50	50	100.00
		kmac_test_vectors_sha3_384	29.541m	1.148s	50	50	100.00
		kmac_test_vectors_sha3_512	18.363m	655.269ms	50	50	100.00
		kmac_test_vectors_shake_128	1.652h	3.429s	50	50	100.00
		kmac_test_vectors_shake_256	1.355h	459.702ms	50	50	100.00
		kmac_test_vectors_kmac	6.510s	4.055ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.990s	1.338ms	50	50	100.00
V2	sideload	kmac_sideload	7.226m	41.900ms	50	50	100.00
V2	app	kmac_app	5.331m	48.185ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.135m	33.556ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.619m	55.082ms	49	50	98.00
V2	error	kmac_error	6.446m	74.087ms	50	50	100.00
V2	key_error	kmac_key_error	10.680s	3.670ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.960s	1.580ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	50.400s	4.683ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.107m	8.233ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	35.930s	2.269ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.402m	236.045ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.850s	13.830us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	97.811us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.760s	610.973us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.760s	610.973us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	287.369us	5	5	100.00
		kmac_csr_rw	1.220s	27.622us	20	20	100.00
		kmac_csr_aliasing	10.160s	527.953us	5	5	100.00
		kmac_same_csr_outstanding	2.660s	173.082us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	287.369us	5	5	100.00
		kmac_csr_rw	1.220s	27.622us	20	20	100.00
		kmac_csr_aliasing	10.160s	527.953us	5	5	100.00
		kmac_same_csr_outstanding	2.660s	173.082us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.360s	51.762us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.360s	51.762us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.360s	51.762us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.360s	51.762us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.200s	164.327us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	54.280s	12.199ms	5	5	100.00
		kmac_tl_intg_err	5.610s	2.026ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.610s	2.026ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	35.930s	2.269ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.080m	36.172ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.226m	41.900ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.360s	51.762us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.280s	12.199ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.280s	12.199ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.280s	12.199ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.080m	36.172ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	35.930s	2.269ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.280s	12.199ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.617m	38.281ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.080m	36.172ms	50	50	100.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	20.247m	95.631ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1233	1250	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.30	95.89	92.27	100.00	68.60	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 1.kmac_stress_all_with_rand_reset.86417885516013032469078973375013752761540810877605307084736790264892180749436
    Line 580, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 163947417947 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 163947417947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.98642844441262455359042499877221192231327124429158326083454191601966288400009
    Line 436, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20925364873 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20925364873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_entropy_refresh has 1 failures.

1.kmac_entropy_refresh.29742118602303766923651553931839538210349451581640072482929278374053082546335
Line 531, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 14019610012 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (33 [0x21] vs 156 [0x9c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14019610012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

4.kmac_mubi.29608159272687639597326586229187195430938242098440996972114748921105157284456
Line 355, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_mubi/latest/run.log

  UVM_FATAL @ 2032588473 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (86 [0x56] vs 221 [0xdd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2032588473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

5.kmac_app.86224546584825938625069799505054122218304381263535905062141411289321032468807
Line 397, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app/latest/run.log

  UVM_FATAL @ 9336897646 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (34 [0x22] vs 233 [0xe9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9336897646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

21.kmac_stress_all.67661113784044383856444068050982754924287994266063701298533897131391792494672
Line 489, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest/run.log

  UVM_FATAL @ 14885146031 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (17 [0x11] vs 161 [0xa1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14885146031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.kmac_stress_all.28368887162300821556551849869449368818722359536844402571184513937022337936741
Line 339, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest/run.log

  UVM_FATAL @ 6339975660 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (243 [0xf3] vs 36 [0x24]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6339975660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 2 failures:

Test kmac_shadow_reg_errors has 2 failures.

6.kmac_shadow_reg_errors.38506884259409717609132276613044003867851377534688577091156749180552116238049
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  11884767 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  11884767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_shadow_reg_errors.113145908801502252587205517395727089181492232319596129339755923819558630031210
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @ 124246995 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 124246995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 12.kmac_shadow_reg_errors_with_csr_rw.12119697567849549286239913899896318754833709173669542188271426931012749863558
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  36123675 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1399349459 [0x536860d3] vs 800222142 [0x2fb26bbe]) Regname: kmac_reg_block.prefix_8 reset value: 0x0
  UVM_INFO @  36123675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 45.kmac_burst_write.18860829051864453315168033857542454274760025924734824361982767883631561552018
    Line 909, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```