KMAC/UNMASKED Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.084m	11.280ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.220s	286.270us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	44.034us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.740s	2.886ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.490s	2.145ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.660s	39.752us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	44.034us	20	20	100.00
		kmac_csr_aliasing	10.490s	2.145ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	11.357us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.560s	149.420us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	42.702m	1.098s	50	50	100.00
V2	burst_write	kmac_burst_write	14.234m	74.221ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.972m	197.329ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.774m	385.403ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.886m	585.314ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.599m	706.722ms	50	50	100.00
		kmac_test_vectors_shake_128	1.752h	3.700s	50	50	100.00
		kmac_test_vectors_shake_256	1.297h	1.952s	50	50	100.00
		kmac_test_vectors_kmac	5.650s	1.001ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.390s	1.020ms	50	50	100.00
V2	sideload	kmac_sideload	6.771m	17.675ms	50	50	100.00
V2	app	kmac_app	5.566m	21.754ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.826m	8.433ms	8	10	80.00
V2	entropy_refresh	kmac_entropy_refresh	4.974m	17.009ms	50	50	100.00
V2	error	kmac_error	6.352m	37.761ms	48	50	96.00
V2	key_error	kmac_key_error	13.230s	19.243ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.300s	14.515ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.390s	4.683ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.152m	35.718ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.120s	2.036ms	50	50	100.00
V2	stress_all	kmac_stress_all	55.293m	1.018s	49	50	98.00
V2	intr_test	kmac_intr_test	0.890s	12.242us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	88.158us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.940s	2.339ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.940s	2.339ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.220s	286.270us	5	5	100.00
		kmac_csr_rw	1.230s	44.034us	20	20	100.00
		kmac_csr_aliasing	10.490s	2.145ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	763.750us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.220s	286.270us	5	5	100.00
		kmac_csr_rw	1.230s	44.034us	20	20	100.00
		kmac_csr_aliasing	10.490s	2.145ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	763.750us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.560s	69.245us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.560s	69.245us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.560s	69.245us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.560s	69.245us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.030s	143.334us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.037m	15.516ms	5	5	100.00
		kmac_tl_intg_err	5.860s	2.890ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.860s	2.890ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.120s	2.036ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.084m	11.280ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.771m	17.675ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.560s	69.245us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.037m	15.516ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.037m	15.516ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.037m	15.516ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.084m	11.280ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.120s	2.036ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.037m	15.516ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.319m	46.869ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.084m	11.280ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	13.718m	37.266ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1230	1250	98.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.03	95.89	92.27	100.00	66.94	94.11	98.84	96.15

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.95893327016664129672427570223634585966847019553486316282649723900042629279503
    Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 960929204 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 960929204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.12597809770446964994339564328387428095902100404220378806676862837815339397397
    Line 1074, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49681070915 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 49681070915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors has 3 failures.

0.kmac_shadow_reg_errors.85559961964929210380274914739075918771702553754651487360264168937773155936123
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   6453491 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   6453491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors.22049709785058496690760452994099947359766122189709114432326769113481677006826
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  45395315 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  45395315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

1.kmac_shadow_reg_errors_with_csr_rw.2013868351753544684290422311247442815164092850862376649077959626682208869811
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  91259177 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  91259177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.kmac_shadow_reg_errors_with_csr_rw.110820704616037562098000583813783806579964372717069321025981055041238398335276
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 106937989 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 106937989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_error has 1 failures.

2.kmac_error.87912973693065263472275544964943231399265142517341780165875967100604352561928
Line 659, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_error/latest/run.log

  UVM_FATAL @ 10594465566 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (167 [0xa7] vs 126 [0x7e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10594465566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

5.kmac_app_with_partial_data.101465761013261354449621066714797734715070309479183517532620516146650557340694
Line 301, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 5654749286 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (6 [0x6] vs 93 [0x5d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5654749286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

10.kmac_app.26510444778302949844965571790805472951418131565113842767289280431132517650991
Line 755, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_app/latest/run.log

  UVM_FATAL @ 20561764788 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (126 [0x7e] vs 139 [0x8b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 20561764788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

40.kmac_stress_all.18972931198359402685139913612477711758571567876787887347152332152002522087940
Line 769, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest/run.log

  UVM_FATAL @ 5780298685 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (253 [0xfd] vs 205 [0xcd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5780298685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 3.kmac_stress_all_with_rand_reset.43675279951414560030086729611898393992423396240961618987267354707358127839289
    Line 1714, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37265667882 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 37265667882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.95551947491587028450235636560820775477100663948031037983563384748302082655601
    Line 593, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6375756270 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6375756270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (kmac_scoreboard.sv:1339) [scoreboard] Check failed digest_share*.size() == output_len_bytes (* [*] vs * [*]) Calculated output length(32) doesn't match actual output length(48)! has 1 failures:
- Test kmac_error has 1 failures.
  - 5.kmac_error.23883946965990670476377664706182057818264453805614811952181606915139627892561
    Line 382, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_error/latest/run.log
```
  UVM_FATAL @ 8571335393 ps: (kmac_scoreboard.sv:1339) [uvm_test_top.env.scoreboard] Check failed digest_share0.size() == output_len_bytes (48 [0x30] vs 32 [0x20]) Calculated output length(32) doesn't match actual output length(48)!
  UVM_INFO @ 8571335393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 7.kmac_app_with_partial_data.91717435061755713965089103789330161585487339399723285871655478652484759035399
    Line 828, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```