KMAC/UNMASKED Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.084m	10.648ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	29.806us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	36.572us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.820s	4.946ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.130s	2.067ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.480s	72.409us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	36.572us	20	20	100.00
		kmac_csr_aliasing	10.130s	2.067ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	157.766us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	170.152us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.077m	246.316ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.127m	171.445ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.542m	1.361s	50	50	100.00
		kmac_test_vectors_sha3_256	37.723m	847.042ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.655m	877.595ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.259m	473.214ms	50	50	100.00
		kmac_test_vectors_shake_128	1.491h	1.163s	50	50	100.00
		kmac_test_vectors_shake_256	1.267h	224.076ms	50	50	100.00
		kmac_test_vectors_kmac	6.200s	1.986ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.540s	1.081ms	50	50	100.00
V2	sideload	kmac_sideload	6.883m	42.152ms	50	50	100.00
V2	app	kmac_app	5.816m	104.545ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.360m	44.020ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.780m	14.859ms	49	50	98.00
V2	error	kmac_error	7.196m	118.431ms	50	50	100.00
V2	key_error	kmac_key_error	11.130s	7.408ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	31.660s	9.387ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.350s	2.258ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	54.000s	7.790ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	27.600s	1.205ms	50	50	100.00
V2	stress_all	kmac_stress_all	53.239m	166.434ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.850s	13.397us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	179.381us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.910s	118.340us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.910s	118.340us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	29.806us	5	5	100.00
		kmac_csr_rw	1.190s	36.572us	20	20	100.00
		kmac_csr_aliasing	10.130s	2.067ms	5	5	100.00
		kmac_same_csr_outstanding	2.630s	549.178us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	29.806us	5	5	100.00
		kmac_csr_rw	1.190s	36.572us	20	20	100.00
		kmac_csr_aliasing	10.130s	2.067ms	5	5	100.00
		kmac_same_csr_outstanding	2.630s	549.178us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.400s	89.514us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.400s	89.514us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.400s	89.514us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.400s	89.514us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.000s	109.563us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.031m	13.382ms	5	5	100.00
		kmac_tl_intg_err	4.970s	478.848us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.970s	478.848us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	27.600s	1.205ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.084m	10.648ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.883m	42.152ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.400s	89.514us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.031m	13.382ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.031m	13.382ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.031m	13.382ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.084m	10.648ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	27.600s	1.205ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.031m	13.382ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.290m	12.946ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.084m	10.648ms	50	50	100.00
V2S		TOTAL			72	75	96.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	40.883m	140.515ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1232	1250	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.28	95.89	92.27	100.00	68.60	94.11	98.84	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.7854642729747951803844750381943342920623023999319832427759134790513798009104
    Line 662, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21631344289 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 21631344289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.80063503716348039167378700728727170436920030613418931239245266583640415967789
    Line 274, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 441074573 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 441074573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all has 2 failures.

0.kmac_stress_all.91167622685016364725545628933396992024562359387255696279030205295335986784162
Line 715, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2349225324 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (170 [0xaa] vs 210 [0xd2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2349225324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.kmac_stress_all.109399372323623174786361254579558592126546444004471989397380989532219806762972
Line 2577, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest/run.log

  UVM_FATAL @ 88628499533 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (152 [0x98] vs 140 [0x8c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 88628499533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

42.kmac_app.89104681537461560190471919279822788779609068208477508032674890786849135426979
Line 343, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_app/latest/run.log

  UVM_FATAL @ 3076584453 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (57 [0x39] vs 119 [0x77]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3076584453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

44.kmac_entropy_refresh.69671515594098683455409667755300870931503085362693510603995089928682291939051
Line 607, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 28759060463 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (169 [0xa9] vs 177 [0xb1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 28759060463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

13.kmac_shadow_reg_errors_with_csr_rw.64010995108645254578898454494371818285280354971010474988070881819543755771242
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  38217947 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  38217947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_shadow_reg_errors_with_csr_rw.46178367392491474547315329114805123571124844707667956019079598431350825509295
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 139504445 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 139504445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 1 failures.

18.kmac_shadow_reg_errors.17140888877128516133126397482254623907983931393947424084553389561287749779321
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  18618829 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  18618829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 4.kmac_stress_all_with_rand_reset.39375426213228130084478372939868917747307535549286016963495064753506674831395
    Line 357, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2592330243 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2592330243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.kmac_stress_all_with_rand_reset.50806681087530376599544273328879510519341955666178865440465458414619782429448
    Line 780, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14966889957 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 14966889957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 19.kmac_burst_write.82245508181476293612162667709494811679657816914602825212450130024053625946390
    Line 1018, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.kmac_burst_write.18992931513076173895837010279062054243603150527054491196858639065960202487848
    Line 830, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```