KMAC/UNMASKED Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.156m	8.168ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	21.251us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	153.307us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.810s	12.489ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.140s	6.280ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.770s	347.999us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	153.307us	20	20	100.00
		kmac_csr_aliasing	11.140s	6.280ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	10.910us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.150s	49.917us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.086m	583.224ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.890m	170.844ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.771m	1.198s	50	50	100.00
		kmac_test_vectors_sha3_256	34.000m	96.032ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.608m	470.628ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.266m	175.180ms	50	50	100.00
		kmac_test_vectors_shake_128	1.747h	3.195s	50	50	100.00
		kmac_test_vectors_shake_256	1.349h	2.362s	50	50	100.00
		kmac_test_vectors_kmac	5.510s	1.009ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.300s	4.032ms	50	50	100.00
V2	sideload	kmac_sideload	6.529m	76.153ms	50	50	100.00
V2	app	kmac_app	5.435m	130.382ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.478m	6.545ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.032m	72.457ms	49	50	98.00
V2	error	kmac_error	6.548m	18.155ms	50	50	100.00
V2	key_error	kmac_key_error	10.040s	13.993ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.140s	17.649ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	49.640s	2.226ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	54.060s	8.213ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	49.950s	916.365us	50	50	100.00
V2	stress_all	kmac_stress_all	41.730m	120.513ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.890s	171.453us	50	50	100.00
V2	alert_test	kmac_alert_test	0.850s	25.405us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.370s	174.377us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.370s	174.377us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	21.251us	5	5	100.00
		kmac_csr_rw	1.210s	153.307us	20	20	100.00
		kmac_csr_aliasing	11.140s	6.280ms	5	5	100.00
		kmac_same_csr_outstanding	2.660s	288.567us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	21.251us	5	5	100.00
		kmac_csr_rw	1.210s	153.307us	20	20	100.00
		kmac_csr_aliasing	11.140s	6.280ms	5	5	100.00
		kmac_same_csr_outstanding	2.660s	288.567us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.510s	244.891us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.510s	244.891us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.510s	244.891us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.510s	244.891us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.930s	424.092us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.020m	12.780ms	5	5	100.00
		kmac_tl_intg_err	5.240s	845.327us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.240s	845.327us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	49.950s	916.365us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.156m	8.168ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.529m	76.153ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.510s	244.891us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.020m	12.780ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.020m	12.780ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.020m	12.780ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.156m	8.168ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	49.950s	916.365us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.020m	12.780ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.641m	15.749ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.156m	8.168ms	50	50	100.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.827m	88.626ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1235	1250	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.35	95.89	92.27	100.00	68.60	94.11	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.18581351163394028127464509037556419401994989959255510849155291374471743701192
    Line 1143, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 190801359614 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 190801359614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.39214804111432702126277869361413620670874914503449362804384700974618779462015
    Line 1044, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31883672526 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31883672526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:

Test kmac_shadow_reg_errors has 1 failures.

7.kmac_shadow_reg_errors.31136990571872468406560313701607202341620502252367686874967700611025336035002
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  45112516 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  45112516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

9.kmac_shadow_reg_errors_with_csr_rw.103111274485848457637645569547650405561311328979341837813206250188493630524113
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  32292982 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  32292982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.kmac_shadow_reg_errors_with_csr_rw.63871092044659914186883731398865461577348883407570080568713514557483261870286
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  81503021 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  81503021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 4.kmac_stress_all_with_rand_reset.80597027752444205981018370996217072288574063321901307073272030219956231227256
    Line 989, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 74422997674 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 74422997674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 13.kmac_shadow_reg_errors_with_csr_rw.14678873513172687156505024485791556713317147476502284273680109016186221038538
    Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  85084888 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1571742131 [0x5daee1b3] vs 3409103238 [0xcb32c986]) Regname: kmac_reg_block.prefix_2 reset value: 0x0
  UVM_INFO @  85084888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 27.kmac_burst_write.106196134876791307380262780598577089756540652868671314721050775789007100753223
    Line 770, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 37.kmac_entropy_refresh.39257277250184052644685644202643368524934200207166251285176080143560658940752
    Line 875, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 10736648614 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (29 [0x1d] vs 166 [0xa6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10736648614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```