KMAC/UNMASKED Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.183m	12.036ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	174.944us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.140s	30.230us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.420s	998.472us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.330s	1.531ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.560s	331.388us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.140s	30.230us	20	20	100.00
		kmac_csr_aliasing	9.330s	1.531ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	24.754us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.420s	112.606us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	43.805m	391.684ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.976m	33.869ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.716m	366.885ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.377m	702.832ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.031m	284.752ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.490m	102.441ms	50	50	100.00
		kmac_test_vectors_shake_128	1.543h	911.624ms	50	50	100.00
		kmac_test_vectors_shake_256	1.555h	3.626s	50	50	100.00
		kmac_test_vectors_kmac	5.810s	2.281ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.520s	2.376ms	50	50	100.00
V2	sideload	kmac_sideload	7.753m	22.841ms	50	50	100.00
V2	app	kmac_app	4.998m	77.900ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.425m	56.747ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.587m	19.813ms	49	50	98.00
V2	error	kmac_error	7.520m	105.936ms	50	50	100.00
V2	key_error	kmac_key_error	12.790s	27.103ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.620s	2.846ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	36.070s	1.330ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.371m	16.958ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	22.310s	448.546us	50	50	100.00
V2	stress_all	kmac_stress_all	38.585m	120.750ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.840s	15.885us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	95.196us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.770s	151.933us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.770s	151.933us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	174.944us	5	5	100.00
		kmac_csr_rw	1.140s	30.230us	20	20	100.00
		kmac_csr_aliasing	9.330s	1.531ms	5	5	100.00
		kmac_same_csr_outstanding	2.700s	126.828us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	174.944us	5	5	100.00
		kmac_csr_rw	1.140s	30.230us	20	20	100.00
		kmac_csr_aliasing	9.330s	1.531ms	5	5	100.00
		kmac_same_csr_outstanding	2.700s	126.828us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	751.018us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	751.018us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	751.018us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	751.018us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.840s	138.652us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.106m	9.880ms	5	5	100.00
		kmac_tl_intg_err	5.110s	248.410us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.110s	248.410us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	22.310s	448.546us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.183m	12.036ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.753m	22.841ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	751.018us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.106m	9.880ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.106m	9.880ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.106m	9.880ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.183m	12.036ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	22.310s	448.546us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.106m	9.880ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.348m	47.975ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.183m	12.036ms	50	50	100.00
V2S		TOTAL			72	75	96.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	42.571m	142.146ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1235	1250	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.02	95.91	92.34	100.00	66.12	94.19	99.00	96.58

Failure Buckets

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app has 3 failures.

5.kmac_app.50376296147397842937565828184939324570545795095864807616575038546600011372300
Line 355, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app/latest/run.log

  UVM_FATAL @ 1556153329 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (253 [0xfd] vs 185 [0xb9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1556153329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.kmac_app.1563701726345302305568692741039612212560582112263415753948417918826570614165
Line 393, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_app/latest/run.log

  UVM_FATAL @ 8831404343 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (19 [0x13] vs 107 [0x6b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8831404343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_stress_all has 1 failures.

19.kmac_stress_all.107653726738771079864410799722972922775419465989818475219533786148644468979812
Line 1327, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest/run.log

  UVM_FATAL @ 92526093923 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (127 [0x7f] vs 190 [0xbe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 92526093923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

41.kmac_entropy_refresh.64329652000671058934089546392354784290513781512878706685529881230934855247108
Line 1035, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 11799729562 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (180 [0xb4] vs 117 [0x75]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11799729562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 1.kmac_stress_all_with_rand_reset.107989660833318429588156928870494294033835275053298483134743800012204593895737
    Line 408, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10534844015 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10534844015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.46496905876278222596119119183945030714647822123337716105938594485829424022162
    Line 1322, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10316000501 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10316000501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.
  - 2.kmac_shadow_reg_errors_with_csr_rw.44506425068317371850789152222802870532382910559877730000653746241359367190964
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 130321390 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 130321390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_shadow_reg_errors_with_csr_rw.76667706419463151323446245364627407088483089574415540633322139947135779186799
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  36349740 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  36349740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 5.kmac_stress_all_with_rand_reset.49449226232316830539029793560792035302199769279017600071722502340145165505454
    Line 1167, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51315712360 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 51315712360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.kmac_stress_all_with_rand_reset.85477453699769083378949904392223725724074160122835022152901681828754499875502
    Line 913, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34015139009 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 34015139009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 42.kmac_burst_write.59302373952301209362841158236842639627284456598761999650697601075143579023936
    Line 692, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```