KMAC/UNMASKED Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.098m	18.698ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	35.517us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.170s	53.069us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.610s	6.942ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.040s	2.666ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.910s	83.616us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.170s	53.069us	20	20	100.00
		kmac_csr_aliasing	8.040s	2.666ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	22.578us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.560s	162.877us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.733m	177.333ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.007m	143.468ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.090m	257.461ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.284m	1.291s	50	50	100.00
		kmac_test_vectors_sha3_384	26.691m	289.303ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.925m	706.593ms	50	50	100.00
		kmac_test_vectors_shake_128	1.720h	1.852s	50	50	100.00
		kmac_test_vectors_shake_256	1.490h	2.426s	50	50	100.00
		kmac_test_vectors_kmac	5.250s	260.432us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.340s	253.407us	50	50	100.00
V2	sideload	kmac_sideload	7.021m	85.516ms	50	50	100.00
V2	app	kmac_app	5.151m	21.478ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.221m	38.654ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.513m	37.096ms	49	50	98.00
V2	error	kmac_error	7.120m	15.170ms	50	50	100.00
V2	key_error	kmac_key_error	12.310s	23.325ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.240s	2.495ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.820s	2.414ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	57.370s	25.430ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	49.860s	1.703ms	50	50	100.00
V2	stress_all	kmac_stress_all	46.831m	185.466ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	21.101us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	20.245us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.310s	131.778us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.310s	131.778us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	35.517us	5	5	100.00
		kmac_csr_rw	1.170s	53.069us	20	20	100.00
		kmac_csr_aliasing	8.040s	2.666ms	5	5	100.00
		kmac_same_csr_outstanding	2.760s	396.476us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	35.517us	5	5	100.00
		kmac_csr_rw	1.170s	53.069us	20	20	100.00
		kmac_csr_aliasing	8.040s	2.666ms	5	5	100.00
		kmac_same_csr_outstanding	2.760s	396.476us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	43.889us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	43.889us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	43.889us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	43.889us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.010s	208.799us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.335m	10.814ms	5	5	100.00
		kmac_tl_intg_err	5.450s	335.693us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.450s	335.693us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	49.860s	1.703ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.098m	18.698ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.021m	85.516ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	43.889us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.335m	10.814ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.335m	10.814ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.335m	10.814ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.098m	18.698ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	49.860s	1.703ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.335m	10.814ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.040m	30.771ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.098m	18.698ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	13.958m	261.004ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1238	1250	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.01	95.77	90.51	100.00	68.60	93.67	98.84	96.72

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
  • Test kmac_stress_all_with_rand_reset has 10 failures.

    • 0.kmac_stress_all_with_rand_reset.90432386513749493092090587673611963682253649918886094085115095536012711108422
      Line 579, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7442072233 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7442072233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.60513251234672531207829583618658024466601457730457077708884118239491363498678
      Line 950, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 261003908193 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 261003908193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 21.kmac_entropy_refresh.3690242841959834012909519619899912796294306607733387798788927653545677848114
      Line 829, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 17385698449 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (4 [0x4] vs 11 [0xb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 17385698449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_stress_all has 1 failures.

    • 42.kmac_stress_all.2843394403773590714229894518057929883872697651357970576035259276316219021453
      Line 2601, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest/run.log

        UVM_FATAL @ 127709354080 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (0 [0x0] vs 73 [0x49]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 127709354080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.07_10.34.15
• 2024.07.06_10.41.39
• 2024.07.05_11.06.18
• 2024.07.04_11.15.21
• 2024.07.03_01.48.58
• 2024.07.02_10.44.26
• 2024.07.02_04.13.51