KMAC/UNMASKED Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.228m	35.137ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.070s	51.289us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.160s	107.208us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.860s	2.955ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.400s	396.890us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.420s	37.721us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.160s	107.208us	20	20	100.00
		kmac_csr_aliasing	9.400s	396.890us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	132.358us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	43.807us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.581m	89.884ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.806m	25.700ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.164m	405.584ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.504m	188.308ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.515m	144.289ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.729m	197.518ms	50	50	100.00
		kmac_test_vectors_shake_128	1.559h	1.070s	50	50	100.00
		kmac_test_vectors_shake_256	1.285h	708.623ms	50	50	100.00
		kmac_test_vectors_kmac	5.370s	2.091ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.730s	1.041ms	50	50	100.00
V2	sideload	kmac_sideload	6.894m	4.801ms	50	50	100.00
V2	app	kmac_app	6.478m	179.793ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.481m	13.640ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.763m	79.657ms	49	50	98.00
V2	error	kmac_error	6.945m	37.820ms	50	50	100.00
V2	key_error	kmac_key_error	9.290s	1.888ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.610s	3.521ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	48.720s	9.866ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	56.230s	9.276ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	49.280s	785.953us	50	50	100.00
V2	stress_all	kmac_stress_all	41.409m	112.588ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	22.681us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	31.130us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.680s	887.459us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.680s	887.459us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.070s	51.289us	5	5	100.00
		kmac_csr_rw	1.160s	107.208us	20	20	100.00
		kmac_csr_aliasing	9.400s	396.890us	5	5	100.00
		kmac_same_csr_outstanding	2.570s	94.855us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.070s	51.289us	5	5	100.00
		kmac_csr_rw	1.160s	107.208us	20	20	100.00
		kmac_csr_aliasing	9.400s	396.890us	5	5	100.00
		kmac_same_csr_outstanding	2.570s	94.855us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.370s	62.361us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.370s	62.361us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.370s	62.361us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.370s	62.361us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.310s	761.877us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.181m	11.537ms	5	5	100.00
		kmac_tl_intg_err	4.940s	264.035us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.940s	264.035us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	49.280s	785.953us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.228m	35.137ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.894m	4.801ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.370s	62.361us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.181m	11.537ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.181m	11.537ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.181m	11.537ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.228m	35.137ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	49.280s	785.953us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.181m	11.537ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.278m	19.136ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.228m	35.137ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	26.889m	23.829ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1240	1250	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.30	95.89	92.27	100.00	68.60	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 1.kmac_stress_all_with_rand_reset.10314803805931012263216499877415569996054478753045762556751141147345556609995
    Line 2673, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23828693136 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 23828693136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.66281450939850692433379852886537480311188438568029620919515109155769769217522
    Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7139709697 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7139709697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_app has 1 failures.
  - 31.kmac_app.106369423224355677306851018485752380269674283758663395554271519476037344508516
    Line 1012, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 40.kmac_entropy_refresh.16991054087542160065850315012084063043937196527359720162765905181210104823493
    Line 886, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 42.kmac_stress_all.100045556098158020236387332227505591087641040503016038083545288438146708042293
    Line 1573, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 246615868072 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (13 [0xd] vs 47 [0x2f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 246615868072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/UNMASKED Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `6a84251492`