KMAC/UNMASKED Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	56.940s	32.566ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.220s	104.947us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	42.401us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.780s	1.451ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.490s	544.378us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	92.999us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	42.401us	20	20	100.00
		kmac_csr_aliasing	9.490s	544.378us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	13.694us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	41.388us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.358m	131.959ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.726m	37.250ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.466m	424.327ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.406m	898.573ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.779m	355.888ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.045m	307.229ms	50	50	100.00
		kmac_test_vectors_shake_128	1.475h	1.071s	50	50	100.00
		kmac_test_vectors_shake_256	1.287h	229.991ms	50	50	100.00
		kmac_test_vectors_kmac	5.510s	274.050us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.770s	269.929us	50	50	100.00
V2	sideload	kmac_sideload	7.509m	54.495ms	50	50	100.00
V2	app	kmac_app	6.306m	13.809ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.172m	32.740ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.806m	75.837ms	50	50	100.00
V2	error	kmac_error	7.458m	88.990ms	50	50	100.00
V2	key_error	kmac_key_error	12.750s	23.337ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.170s	9.028ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	36.380s	1.147ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.225m	88.247ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.039m	1.962ms	50	50	100.00
V2	stress_all	kmac_stress_all	26.579m	99.166ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	18.566us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	84.680us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.330s	255.215us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.330s	255.215us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.220s	104.947us	5	5	100.00
		kmac_csr_rw	1.230s	42.401us	20	20	100.00
		kmac_csr_aliasing	9.490s	544.378us	5	5	100.00
		kmac_same_csr_outstanding	3.290s	2.231ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.220s	104.947us	5	5	100.00
		kmac_csr_rw	1.230s	42.401us	20	20	100.00
		kmac_csr_aliasing	9.490s	544.378us	5	5	100.00
		kmac_same_csr_outstanding	3.290s	2.231ms	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.530s	155.014us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.530s	155.014us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.530s	155.014us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.530s	155.014us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.620s	366.828us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	54.870s	11.449ms	5	5	100.00
		kmac_tl_intg_err	6.220s	2.388ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.220s	2.388ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.039m	1.962ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	56.940s	32.566ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.509m	54.495ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.530s	155.014us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.870s	11.449ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.870s	11.449ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.870s	11.449ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	56.940s	32.566ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.039m	1.962ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.870s	11.449ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.376m	54.388ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	56.940s	32.566ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	29.299m	1.141s	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1239	1250	99.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.07	95.89	92.27	100.00	66.94	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.51933049319787075962965054937530389767377767352170318515707983137430813114587
    Line 325, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20195430726 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20195430726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.23838775245624117540408623565725869887023350109908579986570008052018731426654
    Line 580, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26509501809 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26509501809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.33584352723691832372239572572357959402486233641685686894657392179488616776622
    Line 490, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32681353025 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 32681353025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 8.kmac_key_error.79632534480646605238701806319137583343333293251915255536588200927447172326658
    Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 832990455 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 832990455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_app has 1 failures.
  - 38.kmac_app.31760273915606419961722972997663963475300994138656315402078217760864140560034
    Line 787, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_app/latest/run.log
```
  UVM_FATAL @ 6611313182 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (43 [0x2b] vs 190 [0xbe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6611313182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/UNMASKED Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `39211701b5`