KMAC/UNMASKED Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.292m	27.170ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	125.430us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	44.773us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.570s	5.752ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.640s	2.747ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.600s	86.113us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	44.773us	20	20	100.00
		kmac_csr_aliasing	9.640s	2.747ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	12.684us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	272.276us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.315m	129.585ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.180m	34.409ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.905m	402.909ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.239m	92.105ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.973m	251.185ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.121m	199.664ms	50	50	100.00
		kmac_test_vectors_shake_128	1.619h	1.029s	50	50	100.00
		kmac_test_vectors_shake_256	1.427h	1.673s	50	50	100.00
		kmac_test_vectors_kmac	5.410s	1.133ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.910s	1.082ms	50	50	100.00
V2	sideload	kmac_sideload	7.244m	164.931ms	50	50	100.00
V2	app	kmac_app	5.148m	8.269ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.070m	10.694ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.009m	88.258ms	48	50	96.00
V2	error	kmac_error	6.622m	13.756ms	50	50	100.00
V2	key_error	kmac_key_error	9.580s	7.724ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.460s	3.138ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.470s	2.159ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.430m	36.103ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	35.180s	2.532ms	50	50	100.00
V2	stress_all	kmac_stress_all	36.414m	95.909ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	16.868us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	30.067us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.160s	621.075us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.160s	621.075us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	125.430us	5	5	100.00
		kmac_csr_rw	1.250s	44.773us	20	20	100.00
		kmac_csr_aliasing	9.640s	2.747ms	5	5	100.00
		kmac_same_csr_outstanding	2.610s	225.293us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	125.430us	5	5	100.00
		kmac_csr_rw	1.250s	44.773us	20	20	100.00
		kmac_csr_aliasing	9.640s	2.747ms	5	5	100.00
		kmac_same_csr_outstanding	2.610s	225.293us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.510s	361.632us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.510s	361.632us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.510s	361.632us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.510s	361.632us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.940s	1.095ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.088m	10.213ms	5	5	100.00
		kmac_tl_intg_err	6.340s	2.982ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.340s	2.982ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	35.180s	2.532ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.292m	27.170ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.244m	164.931ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.510s	361.632us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.088m	10.213ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.088m	10.213ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.088m	10.213ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.292m	27.170ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	35.180s	2.532ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.088m	10.213ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.621m	25.601ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.292m	27.170ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.796m	247.804ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1237	1250	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.96	95.89	92.30	100.00	66.12	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.96020280118517725110154598623190372160546470827207443516976162069921343054309
    Line 1099, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 188664770527 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 188664770527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.93441977366661997048344413738681745233274293262488461057258696763657777413477
    Line 543, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17391572208 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17391572208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app_with_partial_data has 1 failures.

0.kmac_app_with_partial_data.81532174286152254190225441102095812958350270360187128823136719459491999404834
Line 549, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 19302461237 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (197 [0xc5] vs 82 [0x52]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 19302461237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

30.kmac_entropy_refresh.104163646746881808156481343470624671072369848593684450576749816738339674891329
Line 561, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5840763768 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (172 [0xac] vs 125 [0x7d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5840763768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.kmac_entropy_refresh.51345533396093784698566974383435694642754304669425879362762082241050103539433
Line 903, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 43323879044 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (118 [0x76] vs 127 [0x7f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 43323879044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.96992923257560594972378911664513392480459037907868811317579930751407168594085
    Line 3982, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 247804301113 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 247804301113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 15.kmac_burst_write.7050967248092308956319308409865260908818856655083025692292966060446586188042
    Line 692, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 22.kmac_key_error.31790123861185918960517972778864268108098982977303947939964615675711893221854
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1217843821 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1217843821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```