KMAC/UNMASKED Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.101m	3.909ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	61.181us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	306.585us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	24.840s	9.586ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.340s	1.525ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.510s	84.148us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	306.585us	20	20	100.00
		kmac_csr_aliasing	9.340s	1.525ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	12.627us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	70.442us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.227m	65.101ms	43	50	86.00
V2	burst_write	kmac_burst_write	19.571m	155.382ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	58.846m	200.300ms	49	50	98.00
		kmac_test_vectors_sha3_256	57.604m	552.932ms	50	50	100.00
		kmac_test_vectors_sha3_384	41.189m	638.545ms	50	50	100.00
		kmac_test_vectors_sha3_512	26.654m	198.224ms	50	50	100.00
		kmac_test_vectors_shake_128	1.565h	61.785ms	16	50	32.00
		kmac_test_vectors_shake_256	1.280h	88.711ms	24	50	48.00
		kmac_test_vectors_kmac	5.780s	852.149us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.700s	436.269us	50	50	100.00
V2	sideload	kmac_sideload	8.058m	21.231ms	50	50	100.00
V2	app	kmac_app	6.414m	84.806ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.381m	162.634ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.243m	16.219ms	49	50	98.00
V2	error	kmac_error	7.769m	79.497ms	50	50	100.00
V2	key_error	kmac_key_error	9.690s	1.892ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.470s	1.400ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.350s	8.240ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.045m	4.635ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	35.730s	3.953ms	50	50	100.00
V2	stress_all	kmac_stress_all	37.659m	126.900ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.860s	24.713us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	126.613us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.860s	448.120us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.860s	448.120us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	61.181us	5	5	100.00
		kmac_csr_rw	1.190s	306.585us	20	20	100.00
		kmac_csr_aliasing	9.340s	1.525ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	1.226ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	61.181us	5	5	100.00
		kmac_csr_rw	1.190s	306.585us	20	20	100.00
		kmac_csr_aliasing	9.340s	1.525ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	1.226ms	20	20	100.00
V2		TOTAL			979	1050	93.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.500s	101.863us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.500s	101.863us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.500s	101.863us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.500s	101.863us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.080s	199.898us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.256m	11.818ms	5	5	100.00
		kmac_tl_intg_err	5.100s	186.789us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.100s	186.789us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	35.730s	3.953ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.101m	3.909ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.058m	21.231ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.500s	101.863us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.256m	11.818ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.256m	11.818ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.256m	11.818ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.101m	3.909ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	35.730s	3.953ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.256m	11.818ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.928m	60.211ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.101m	3.909ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	32.438m	82.505ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1169	1250	93.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.42	95.89	92.27	100.00	69.42	94.11	98.84	96.43

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 68 failures:
- Test kmac_test_vectors_shake_128 has 34 failures.
  - 0.kmac_test_vectors_shake_128.41897178343100654039301347484311725871619890176615278563859144738305050615367
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:c0ae1982-fe1c-4bdd-9e5d-b81bf56a0c81
```
  - 1.kmac_test_vectors_shake_128.108082261410684390462462811150382557337907191873113241382263348158105876289063
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:a0015dbe-1a10-48e1-8aaf-8967b5a0e05d
```
  - ... and 32 more failures.
- Test kmac_test_vectors_shake_256 has 26 failures.
  - 0.kmac_test_vectors_shake_256.96230805649452066179465319068800733515542874683148441880591109372309122437810
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:803a7745-ab30-45a5-9755-7f697a2f0198
```
  - 1.kmac_test_vectors_shake_256.77760167014617218549141929224736336218651044856480181407532207716535151861301
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:201a7875-0b1a-44c8-a027-50c6d75d2509
```
  - ... and 24 more failures.
- Test kmac_long_msg_and_output has 7 failures.
  - 2.kmac_long_msg_and_output.66507524464635881072315092538073401278234884210327720650614980196477522406470
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:05a28cfb-25c2-4e70-bd48-a5f9d85b4067
```
  - 3.kmac_long_msg_and_output.71302959973254689508234977102883677383445082753526133729879666194900767057273
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:7de85584-97ff-412c-ae88-6ec85c57061a
```
  - ... and 5 more failures.
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 47.kmac_test_vectors_sha3_224.40923623157988813907751974855852773545674487256524447208585638475217131101368
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:82ae3f28-6981-4560-ad62-6f9d151bac6a
```
UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.56056824079409020411270541986879427845965353066801047536715223106802243909057
    Line 1060, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32491295549 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 32491295549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.114715635903835131059746676559117924448344945816764269226519513377947929011012
    Line 323, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1483842916 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1483842916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all has 2 failures.

0.kmac_stress_all.88900174256347885214193620877283622621544216527099404263625648218142137717765
Line 1467, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest/run.log

  UVM_FATAL @ 15843393176 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (97 [0x61] vs 157 [0x9d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 15843393176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_stress_all.26221232569153536266522533428164949668351422600483536804066034144370749239905
Line 2447, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest/run.log

  UVM_FATAL @ 17948002932 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (111 [0x6f] vs 100 [0x64]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17948002932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

5.kmac_entropy_refresh.98051558598723533003408364852930791009993235274014235137956717734436390347971
Line 581, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6366509443 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (130 [0x82] vs 166 [0xa6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6366509443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 7.kmac_stress_all_with_rand_reset.102209851887167032793498844501421040702567758182838794065907356779947767493962
    Line 536, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53377220140 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 53377220140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.kmac_stress_all_with_rand_reset.22278295875089242374404575637220346341164826211195291995272319424640677047165
    Line 2501, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 656127209186 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 656127209186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_mubi has 1 failures.
  - 6.kmac_mubi.58113265267299945753221434520338435905866240498036712779822434067785872434923
    Line 805, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```