KMAC/UNMASKED Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.259m	48.675ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	37.569us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.170s	119.184us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	17.920s	990.705us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.640s	503.161us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.550s	74.545us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.170s	119.184us	20	20	100.00
		kmac_csr_aliasing	9.640s	503.161us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	14.401us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	315.700us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	44.505m	570.515ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.580m	124.739ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.127m	810.452ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.496m	419.816ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.452m	365.774ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.103m	206.050ms	50	50	100.00
		kmac_test_vectors_shake_128	1.531h	507.137ms	50	50	100.00
		kmac_test_vectors_shake_256	1.336h	2.399s	50	50	100.00
		kmac_test_vectors_kmac	5.390s	972.808us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.690s	1.010ms	50	50	100.00
V2	sideload	kmac_sideload	8.264m	190.256ms	50	50	100.00
V2	app	kmac_app	5.109m	46.572ms	46	50	92.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.811m	31.035ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.802m	8.845ms	50	50	100.00
V2	error	kmac_error	6.931m	40.049ms	49	50	98.00
V2	key_error	kmac_key_error	10.320s	7.986ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.180s	4.458ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.280s	9.668ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.259m	9.399ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.910s	1.164ms	50	50	100.00
V2	stress_all	kmac_stress_all	53.206m	309.211ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.830s	21.456us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	28.503us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.120s	209.777us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.120s	209.777us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	37.569us	5	5	100.00
		kmac_csr_rw	1.170s	119.184us	20	20	100.00
		kmac_csr_aliasing	9.640s	503.161us	5	5	100.00
		kmac_same_csr_outstanding	2.490s	110.823us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	37.569us	5	5	100.00
		kmac_csr_rw	1.170s	119.184us	20	20	100.00
		kmac_csr_aliasing	9.640s	503.161us	5	5	100.00
		kmac_same_csr_outstanding	2.490s	110.823us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.360s	193.793us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.360s	193.793us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.360s	193.793us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.360s	193.793us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.870s	495.085us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	54.650s	3.221ms	5	5	100.00
		kmac_tl_intg_err	4.830s	326.868us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.830s	326.868us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.910s	1.164ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.259m	48.675ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.264m	190.256ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.360s	193.793us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.650s	3.221ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.650s	3.221ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.650s	3.221ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.259m	48.675ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.910s	1.164ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.650s	3.221ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.566m	44.657ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.259m	48.675ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	21.823m	333.734ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1235	1250	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.07	95.89	92.27	100.00	66.94	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.67889404394328782704880823828849583563653707734800049468491417009405049015671
    Line 406, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11550339847 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11550339847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.87662471947769506069308741145888361741779792543566351876499164955972273315455
    Line 317, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1026079643 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1026079643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_mubi has 1 failures.

9.kmac_mubi.62249852065887875503339677925161636292328606297898763307797565461884502860722
Line 629, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_mubi/latest/run.log

  UVM_FATAL @ 9502559947 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (147 [0x93] vs 56 [0x38]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9502559947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 4 failures.

16.kmac_app.27639519005257035414030769693112806885051741535485332114157873696934460084130
Line 437, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_app/latest/run.log

  UVM_FATAL @ 7107951694 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (160 [0xa0] vs 128 [0x80]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7107951694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.kmac_app.115220616469862876393316545816220016352079509171565945855667486217842620378654
Line 857, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_app/latest/run.log

  UVM_FATAL @ 139090258267 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (82 [0x52] vs 204 [0xcc]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 139090258267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 6.kmac_stress_all_with_rand_reset.96188823621241356501846240690032163849101708478101962245594201966505549617478
    Line 315, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3340253958 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3340253958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.99890983279203654056970127838939824611080397261224380115798601793533820784026
    Line 886, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21694008086 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 21694008086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 25.kmac_error.76094276979938754622755722537940655057603028935293714552846867270057568102328
    Line 1375, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```