KMAC/UNMASKED Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.155m	17.314ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	67.494us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.150s	38.459us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.820s	293.579us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.190s	230.006us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	134.677us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.150s	38.459us	20	20	100.00
		kmac_csr_aliasing	8.190s	230.006us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	21.652us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.420s	56.203us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.637m	777.923ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.732m	74.791ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.845m	655.140ms	50	50	100.00
		kmac_test_vectors_sha3_256	37.849m	1.325s	50	50	100.00
		kmac_test_vectors_sha3_384	28.420m	1.397s	50	50	100.00
		kmac_test_vectors_sha3_512	19.127m	194.459ms	50	50	100.00
		kmac_test_vectors_shake_128	1.705h	2.340s	50	50	100.00
		kmac_test_vectors_shake_256	1.455h	2.696s	50	50	100.00
		kmac_test_vectors_kmac	5.750s	2.739ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.640s	521.375us	50	50	100.00
V2	sideload	kmac_sideload	6.604m	18.551ms	50	50	100.00
V2	app	kmac_app	6.454m	157.115ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.382m	40.518ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.981m	163.102ms	50	50	100.00
V2	error	kmac_error	7.785m	200.000ms	49	50	98.00
V2	key_error	kmac_key_error	11.250s	12.198ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.870s	7.836ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	52.950s	34.341ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.229m	53.305ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.870s	2.381ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.672m	151.974ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.840s	29.147us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	137.029us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.390s	132.866us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.390s	132.866us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	67.494us	5	5	100.00
		kmac_csr_rw	1.150s	38.459us	20	20	100.00
		kmac_csr_aliasing	8.190s	230.006us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	483.545us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	67.494us	5	5	100.00
		kmac_csr_rw	1.150s	38.459us	20	20	100.00
		kmac_csr_aliasing	8.190s	230.006us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	483.545us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.470s	65.763us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.470s	65.763us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.470s	65.763us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.470s	65.763us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.560s	128.808us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.177m	22.146ms	5	5	100.00
		kmac_tl_intg_err	5.130s	252.820us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.130s	252.820us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.870s	2.381ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.155m	17.314ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.604m	18.551ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.470s	65.763us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.177m	22.146ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.177m	22.146ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.177m	22.146ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.155m	17.314ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.870s	2.381ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.177m	22.146ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.718m	40.039ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.155m	17.314ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.827m	29.621ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1239	1250	99.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.74	95.89	92.30	100.00	64.46	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.113261747587578677870793309694559840211848785119730689844868895530543154627374
    Line 3429, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29620581372 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 29620581372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.115071996766919197388821966590803300014516432821073153380790705238673423785935
    Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 224848765 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 224848765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 1.kmac_stress_all_with_rand_reset.59496109576154481289263940919775758144274618275214565760714795451682735844251
    Line 1412, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24768046748 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 24768046748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.29808373233328678806879175302873346156003922681808988330655765209022732989237
    Line 1734, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 67072261017 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 67072261017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_app has 2 failures.

10.kmac_app.24812167349048043020715209386100774343689049374690941415493249655518658545218
Line 533, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_app/latest/run.log

  UVM_FATAL @ 16453041665 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (154 [0x9a] vs 223 [0xdf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16453041665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.kmac_app.81047911383916281705379972041171895268682797993768634343863996565976571074859
Line 375, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_app/latest/run.log

  UVM_FATAL @ 10667662960 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (157 [0x9d] vs 217 [0xd9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10667662960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 32.kmac_error.50352977332989727730294388149536983346764168840153090856784996703798668137624
    Line 1307, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```