KMAC/UNMASKED Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.123m	5.822ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	40.111us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.160s	29.200us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.450s	6.012ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.330s	2.511ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	77.821us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.160s	29.200us	20	20	100.00
		kmac_csr_aliasing	9.330s	2.511ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	19.501us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	202.050us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.543m	1.018s	50	50	100.00
V2	burst_write	kmac_burst_write	14.405m	35.543ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.661m	392.707ms	50	50	100.00
		kmac_test_vectors_sha3_256	37.865m	899.782ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.869m	430.072ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.729m	191.848ms	50	50	100.00
		kmac_test_vectors_shake_128	1.564h	533.596ms	50	50	100.00
		kmac_test_vectors_shake_256	1.398h	1.347s	50	50	100.00
		kmac_test_vectors_kmac	5.220s	1.078ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.410s	994.657us	50	50	100.00
V2	sideload	kmac_sideload	7.694m	43.865ms	50	50	100.00
V2	app	kmac_app	5.008m	48.850ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.791m	7.332ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.924m	21.362ms	49	50	98.00
V2	error	kmac_error	6.333m	19.616ms	50	50	100.00
V2	key_error	kmac_key_error	14.170s	17.250ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.580s	15.855ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.840s	4.977ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.083m	7.678ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	34.970s	1.657ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.812m	89.046ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.840s	39.824us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	256.473us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.980s	976.566us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.980s	976.566us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	40.111us	5	5	100.00
		kmac_csr_rw	1.160s	29.200us	20	20	100.00
		kmac_csr_aliasing	9.330s	2.511ms	5	5	100.00
		kmac_same_csr_outstanding	2.380s	216.081us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	40.111us	5	5	100.00
		kmac_csr_rw	1.160s	29.200us	20	20	100.00
		kmac_csr_aliasing	9.330s	2.511ms	5	5	100.00
		kmac_same_csr_outstanding	2.380s	216.081us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.520s	139.527us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.520s	139.527us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.520s	139.527us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.520s	139.527us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.040s	559.980us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.137m	42.492ms	5	5	100.00
		kmac_tl_intg_err	5.070s	1.078ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.070s	1.078ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	34.970s	1.657ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.123m	5.822ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.694m	43.865ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.520s	139.527us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.137m	42.492ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.137m	42.492ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.137m	42.492ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.123m	5.822ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	34.970s	1.657ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.137m	42.492ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.423m	17.686ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.123m	5.822ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	24.282m	32.883ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1239	1250	99.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.74	95.89	92.30	100.00	64.46	94.11	98.84	96.58

Failure Buckets

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 2 failures.

1.kmac_app.80314915766915740498219268960471278506545965008811706239921354147455993202176
Line 417, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app/latest/run.log

  UVM_FATAL @ 2159966029 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (7 [0x7] vs 254 [0xfe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2159966029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.kmac_app.44837742833101320791600711253828872160931269679552920862425596330336406545374
Line 795, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_app/latest/run.log

  UVM_FATAL @ 2392021646 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (17 [0x11] vs 190 [0xbe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2392021646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

1.kmac_entropy_refresh.104810528135739565378861157267380023573734192564824763276436242178429632589865
Line 415, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3337460992 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (152 [0x98] vs 240 [0xf0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3337460992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

14.kmac_stress_all.114935564984151776862964244519402985699001192708315436334732057466955351268750
Line 2353, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest/run.log

  UVM_FATAL @ 172038625794 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (196 [0xc4] vs 61 [0x3d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 172038625794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 3.kmac_stress_all_with_rand_reset.85791182479754753069467269101900411006177548520848810889578906198247323048092
    Line 759, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 82670856574 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 82670856574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.25833659552755100829105118630240228954989688776461039148558098846850591549183
    Line 1041, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131948879196 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 131948879196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 1.kmac_stress_all_with_rand_reset.15878006109452103763265228775454666957338951930557593125303892782431791165265
    Line 273, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 259310791 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 259310791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.2315522629370133832580449747883614512842101446639401011077520414060631792003
    Line 462, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27401972956 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 27401972956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.