KMAC/UNMASKED Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.199m	29.603ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.230s	326.131us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	27.052us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.410s	285.481us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.000s	1.528ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.630s	105.117us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	27.052us	20	20	100.00
		kmac_csr_aliasing	9.000s	1.528ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	28.971us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.340s	31.667us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.648m	712.194ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.818m	131.030ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.565m	950.773ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.365m	94.181ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.456m	545.942ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.918m	410.951ms	50	50	100.00
		kmac_test_vectors_shake_128	1.579h	3.426s	50	50	100.00
		kmac_test_vectors_shake_256	1.353h	1.658s	50	50	100.00
		kmac_test_vectors_kmac	5.450s	473.407us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.850s	2.693ms	50	50	100.00
V2	sideload	kmac_sideload	7.504m	121.088ms	50	50	100.00
V2	app	kmac_app	5.615m	12.418ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.211m	16.073ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.719m	75.564ms	50	50	100.00
V2	error	kmac_error	6.807m	23.895ms	50	50	100.00
V2	key_error	kmac_key_error	9.870s	6.762ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.450s	1.615ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.660s	14.594ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.089m	58.784ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.100s	679.118us	50	50	100.00
V2	stress_all	kmac_stress_all	41.197m	88.518ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.860s	19.129us	50	50	100.00
V2	alert_test	kmac_alert_test	1.000s	192.155us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.650s	550.242us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.650s	550.242us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.230s	326.131us	5	5	100.00
		kmac_csr_rw	1.180s	27.052us	20	20	100.00
		kmac_csr_aliasing	9.000s	1.528ms	5	5	100.00
		kmac_same_csr_outstanding	2.550s	393.246us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.230s	326.131us	5	5	100.00
		kmac_csr_rw	1.180s	27.052us	20	20	100.00
		kmac_csr_aliasing	9.000s	1.528ms	5	5	100.00
		kmac_same_csr_outstanding	2.550s	393.246us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	58.581us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	58.581us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	58.581us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	58.581us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.300s	1.418ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.428m	23.092ms	5	5	100.00
		kmac_tl_intg_err	5.200s	418.886us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.200s	418.886us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.100s	679.118us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.199m	29.603ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.504m	121.088ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	58.581us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.428m	23.092ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.428m	23.092ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.428m	23.092ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.199m	29.603ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.100s	679.118us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.428m	23.092ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.506m	44.070ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.199m	29.603ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	12.613m	132.104ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1234	1250	98.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.62	95.77	90.51	100.00	66.12	93.67	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 0.kmac_stress_all_with_rand_reset.82321223565807757366579629882970441580618216809232307491847920855206942519089
    Line 893, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38269775592 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 38269775592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.38385440622932496836034998916212011911785258615119961066240632809277286838956
    Line 420, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12613744083 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12613744083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 3 failures.
  - 2.kmac_burst_write.42834988836658703626236476125621822472226260393835386680418586128888840497656
    Line 663, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_burst_write.93477358141140637793087462807929454519296226302777944132214078015798907571976
    Line 1208, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_app has 1 failures.
  - 33.kmac_app.73368141642072169393459432650592052335157691282989708990701444866146390906371
    Line 776, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_stress_all has 2 failures.

5.kmac_stress_all.100462815202937168063096313670627749392474779501674103299818814316843157243271
Line 1447, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest/run.log

  UVM_FATAL @ 5173046568 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (117 [0x75] vs 64 [0x40]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5173046568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.kmac_stress_all.53819464759169120529110749671256448269638113590205207998541714976956727964320
Line 2049, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest/run.log

  UVM_FATAL @ 51215737770 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (3 [0x3] vs 130 [0x82]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 51215737770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 1.kmac_stress_all_with_rand_reset.95235031268511816946914080176978362685300464144108087467180599002086854749558
    Line 874, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 60629098010 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 60629098010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```