KMAC/UNMASKED Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.220m	4.327ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	66.339us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	139.194us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.430s	1.482ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.630s	3.994ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	153.835us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	139.194us	20	20	100.00
		kmac_csr_aliasing	9.630s	3.994ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	31.671us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.290s	372.645us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.399m	2.050s	50	50	100.00
V2	burst_write	kmac_burst_write	14.135m	93.678ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.572m	1.073s	50	50	100.00
		kmac_test_vectors_sha3_256	35.095m	891.014ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.625m	431.989ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.906m	380.925ms	50	50	100.00
		kmac_test_vectors_shake_128	1.453h	1.721s	50	50	100.00
		kmac_test_vectors_shake_256	1.283h	1.358s	50	50	100.00
		kmac_test_vectors_kmac	5.900s	2.262ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.590s	907.975us	50	50	100.00
V2	sideload	kmac_sideload	7.315m	166.882ms	50	50	100.00
V2	app	kmac_app	5.376m	131.619ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.116m	152.751ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.552m	27.573ms	47	50	94.00
V2	error	kmac_error	6.785m	187.090ms	50	50	100.00
V2	key_error	kmac_key_error	12.010s	16.049ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.710s	5.982ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.270s	5.028ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.068m	26.805ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	27.890s	1.082ms	50	50	100.00
V2	stress_all	kmac_stress_all	39.508m	318.260ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.840s	15.689us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	16.703us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.410s	480.470us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.410s	480.470us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	66.339us	5	5	100.00
		kmac_csr_rw	1.200s	139.194us	20	20	100.00
		kmac_csr_aliasing	9.630s	3.994ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	129.953us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	66.339us	5	5	100.00
		kmac_csr_rw	1.200s	139.194us	20	20	100.00
		kmac_csr_aliasing	9.630s	3.994ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	129.953us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.370s	64.387us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.370s	64.387us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.370s	64.387us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.370s	64.387us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.300s	529.676us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.141m	6.114ms	5	5	100.00
		kmac_tl_intg_err	5.510s	334.800us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.510s	334.800us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	27.890s	1.082ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.220m	4.327ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.315m	166.882ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.370s	64.387us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.141m	6.114ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.141m	6.114ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.141m	6.114ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.220m	4.327ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	27.890s	1.082ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.141m	6.114ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.297m	57.949ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.220m	4.327ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	8.164m	19.125ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1237	1250	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.19	95.89	92.30	100.00	67.77	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.111081762503198845174006548597276238030345019320309808279129479694426132547092
    Line 948, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5425624879 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5425624879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.9351028886441441256389720296614243008526739111223949727257521532429407076726
    Line 426, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3082067145 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3082067145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_entropy_refresh has 3 failures.

2.kmac_entropy_refresh.7627632163703709855176042282418621851672493223509636103682346381363640402835
Line 377, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5182430644 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (120 [0x78] vs 98 [0x62]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5182430644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.kmac_entropy_refresh.442018625435057058939772341904634313819150394404282505125289232005681323855
Line 353, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 887913536 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (47 [0x2f] vs 45 [0x2d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 887913536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_stress_all has 1 failures.

21.kmac_stress_all.56437429262144452876401145146540913245575082461476400375333099110012078735652
Line 935, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest/run.log

  UVM_FATAL @ 7844587069 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (80 [0x50] vs 222 [0xde]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7844587069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 3.kmac_stress_all_with_rand_reset.22150857734575261474957501363481802164019105778312129872830808585594188341912
    Line 546, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 209368404538 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 209368404538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 38.kmac_burst_write.10169347128793025143616763842488182890853617874212128694094451045281854964892
    Line 718, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```