KMAC/UNMASKED Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.071m	7.299ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	31.771us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	33.431us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.740s	6.963ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.690s	489.382us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.520s	39.702us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	33.431us	20	20	100.00
		kmac_csr_aliasing	9.690s	489.382us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	15.483us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.550s	140.074us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.469m	241.959ms	41	50	82.00
V2	burst_write	kmac_burst_write	17.796m	225.252ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	57.558m	95.587ms	49	50	98.00
		kmac_test_vectors_sha3_256	56.844m	907.061ms	49	50	98.00
		kmac_test_vectors_sha3_384	38.730m	157.980ms	50	50	100.00
		kmac_test_vectors_sha3_512	28.471m	542.378ms	50	50	100.00
		kmac_test_vectors_shake_128	1.612h	211.765ms	17	50	34.00
		kmac_test_vectors_shake_256	1.343h	439.458ms	18	50	36.00
		kmac_test_vectors_kmac	6.020s	862.063us	50	50	100.00
		kmac_test_vectors_kmac_xof	6.010s	1.230ms	50	50	100.00
V2	sideload	kmac_sideload	8.550m	76.659ms	50	50	100.00
V2	app	kmac_app	6.778m	158.598ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.373m	90.483ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.032m	76.552ms	50	50	100.00
V2	error	kmac_error	8.795m	20.397ms	50	50	100.00
V2	key_error	kmac_key_error	12.310s	15.706ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.830s	2.414ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.560s	494.818us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.181m	28.493ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.850s	4.229ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.204h	568.303ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.830s	27.264us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	20.994us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.220s	185.063us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.220s	185.063us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	31.771us	5	5	100.00
		kmac_csr_rw	1.190s	33.431us	20	20	100.00
		kmac_csr_aliasing	9.690s	489.382us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	550.027us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	31.771us	5	5	100.00
		kmac_csr_rw	1.190s	33.431us	20	20	100.00
		kmac_csr_aliasing	9.690s	489.382us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	550.027us	20	20	100.00
V2		TOTAL			970	1050	92.38
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.480s	62.545us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.480s	62.545us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.480s	62.545us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.480s	62.545us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.040s	138.154us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	58.830s	5.113ms	5	5	100.00
		kmac_tl_intg_err	5.440s	291.549us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.440s	291.549us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.850s	4.229ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.071m	7.299ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.550m	76.659ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.480s	62.545us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	58.830s	5.113ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	58.830s	5.113ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	58.830s	5.113ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.071m	7.299ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.850s	4.229ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	58.830s	5.113ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.720m	30.787ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.071m	7.299ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	24.728m	59.371ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1163	1250	93.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.07	95.89	92.27	100.00	66.94	94.11	98.84	96.43

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 76 failures:
- Test kmac_test_vectors_shake_256 has 32 failures.
  - 0.kmac_test_vectors_shake_256.72982756508118576922171930839550247923556676877804453274318633360593814819292
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:5622f800-32b7-4ed0-8713-5432af1f4118
```
  - 3.kmac_test_vectors_shake_256.6365721131975366933117403169569406861950277167840994537292824028276235487584
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:81f2a857-8efb-45e1-884c-566583a90d2a
```
  - ... and 30 more failures.
- Test kmac_test_vectors_shake_128 has 33 failures.
  - 1.kmac_test_vectors_shake_128.110068524976338719725801342320543702140170537078701326422375135698653757961625
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:4780b173-e370-4176-ba8b-303699ad87a0
```
  - 2.kmac_test_vectors_shake_128.104344334181633603852365518734864100408981411623585314901538275171638076644455
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:44555a32-8ece-4ea4-9db3-6a9d67b4f1f8
```
  - ... and 31 more failures.
- Test kmac_long_msg_and_output has 9 failures.
  - 2.kmac_long_msg_and_output.61854429528566988528963312764155012246630111720214863888703123552722575597593
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:79b8e0cb-9ff1-42b4-9f3f-89d043b734e1
```
  - 12.kmac_long_msg_and_output.19249240399667606396342595716987459583746490012192848950673139115107064020805
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:6ea213f0-7ade-42ee-aa81-2325212d73b1
```
  - ... and 7 more failures.
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 24.kmac_test_vectors_sha3_256.58399252858546286436290286438256737690282192790790428952710467627437490123816
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_sha3_256/latest/run.log
```
  Job ID: smart:e211d958-34c4-456d-9554-749c2bac5a30
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 40.kmac_test_vectors_sha3_224.8715512349606628912340658337784707768705832927932286358619407587846180405665
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:42ed35af-db76-4426-bc27-f76939145a0c
```
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.114472704460191569956948843695798920733377720179358102077849376464673706930372
    Line 1103, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 102865397167 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 102865397167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.58640031621388601179291104404396665755758832807070729133831934812536662234799
    Line 1356, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40444120716 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 40444120716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app_with_partial_data has 1 failures.

6.kmac_app_with_partial_data.61375678962383085309801420715239908891262453541723844849423450677265355285139
Line 817, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 27280170391 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (138 [0x8a] vs 241 [0xf1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 27280170391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

7.kmac_app.6630035578144016434114912489091242124036364744854809883405717320695645909554
Line 355, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app/latest/run.log

  UVM_FATAL @ 3042512669 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (109 [0x6d] vs 192 [0xc0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3042512669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.kmac_app.14760366856691856347345802054863055958757112532938283393310094334442505541805
Line 313, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_app/latest/run.log

  UVM_FATAL @ 755207048 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (127 [0x7f] vs 193 [0xc1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 755207048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

20.kmac_stress_all.15645356009850017946230165301023859792698368427970643383371060374541247653393
Line 1997, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest/run.log

  UVM_FATAL @ 91383780469 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (41 [0x29] vs 47 [0x2f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 91383780469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---