KMAC/UNMASKED Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.154m	3.671ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	32.927us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	396.126us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.270s	6.039ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.160s	804.018us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	186.194us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	396.126us	20	20	100.00
		kmac_csr_aliasing	10.160s	804.018us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	15.620us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	41.032us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.215m	343.745ms	38	50	76.00
V2	burst_write	kmac_burst_write	18.511m	125.062ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	58.602m	345.929ms	49	50	98.00
		kmac_test_vectors_sha3_256	56.688m	441.746ms	50	50	100.00
		kmac_test_vectors_sha3_384	40.559m	286.412ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.193m	219.255ms	50	50	100.00
		kmac_test_vectors_shake_128	1.703h	106.500ms	22	50	44.00
		kmac_test_vectors_shake_256	1.358h	181.555ms	23	50	46.00
		kmac_test_vectors_kmac	5.920s	507.666us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.510s	249.620us	50	50	100.00
V2	sideload	kmac_sideload	8.216m	78.936ms	50	50	100.00
V2	app	kmac_app	5.655m	62.021ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.781m	35.334ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.574m	30.487ms	49	50	98.00
V2	error	kmac_error	9.357m	184.298ms	48	50	96.00
V2	key_error	kmac_key_error	8.340s	1.553ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.770s	7.434ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	51.940s	4.716ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.303m	18.639ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	29.930s	561.991us	50	50	100.00
V2	stress_all	kmac_stress_all	48.922m	70.866ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.850s	33.049us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	177.208us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.760s	624.276us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.760s	624.276us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	32.927us	5	5	100.00
		kmac_csr_rw	1.190s	396.126us	20	20	100.00
		kmac_csr_aliasing	10.160s	804.018us	5	5	100.00
		kmac_same_csr_outstanding	2.670s	126.240us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	32.927us	5	5	100.00
		kmac_csr_rw	1.190s	396.126us	20	20	100.00
		kmac_csr_aliasing	10.160s	804.018us	5	5	100.00
		kmac_same_csr_outstanding	2.670s	126.240us	20	20	100.00
V2		TOTAL			975	1050	92.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.490s	631.598us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.490s	631.598us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.490s	631.598us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.490s	631.598us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.830s	420.893us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	52.940s	3.224ms	5	5	100.00
		kmac_tl_intg_err	5.270s	2.622ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.270s	2.622ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	29.930s	561.991us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.154m	3.671ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.216m	78.936ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.490s	631.598us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	52.940s	3.224ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	52.940s	3.224ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	52.940s	3.224ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.154m	3.671ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	29.930s	561.991us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	52.940s	3.224ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.369m	113.777ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.154m	3.671ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	21.202m	58.157ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1166	1250	93.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.07	95.89	92.27	100.00	66.94	94.11	98.84	96.43

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 68 failures:
- Test kmac_long_msg_and_output has 12 failures.
  - 0.kmac_long_msg_and_output.41788179800739400396999692516617943408939017455277323717047580195347831306648
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:5ee08fc3-4cf8-4744-9b0d-57ff29c9e25d
```
  - 2.kmac_long_msg_and_output.17935087042490189935088016420959982345563625777105539840678224291043716157980
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:57febf41-a76d-427e-8c01-9012eefbd929
```
  - ... and 10 more failures.
- Test kmac_test_vectors_shake_128 has 28 failures.
  - 0.kmac_test_vectors_shake_128.68071923675342702730358967733732100265865640868214191589511125197688523555100
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:c2d01c04-3fd8-47fd-a1b9-c0251f533a60
```
  - 2.kmac_test_vectors_shake_128.91471261327336724425773712718637998160394201765256252682962911180063761212053
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:4869cfc9-035e-4cf0-b1b5-980c5b3d524a
```
  - ... and 26 more failures.
- Test kmac_test_vectors_shake_256 has 27 failures.
  - 0.kmac_test_vectors_shake_256.49975713320903666576123180427264321661204395723619476750990022705786813284952
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:5aa2b72d-bae6-4d78-9b69-9489ead7b09c
```
  - 2.kmac_test_vectors_shake_256.41493011320110489642044047790497330860893354693934739864832792117636730882094
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:e818b5c1-79a0-4777-b374-7056f847f001
```
  - ... and 25 more failures.
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 13.kmac_test_vectors_sha3_224.88373713436052860310390937924709578397300837493695956120288489863610963390772
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:1c32240e-9fab-4b6b-980a-46114b92f545
```
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.14624964080029362104436604137878391633888581134936284345258229767819424699128
    Line 510, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7324883806 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7324883806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.19366960663522925495605860046264052911080817599052096576826554751393058265593
    Line 1964, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17951132476 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17951132476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 1 failures.

30.kmac_app.75424373491198055211300436334433761533591520672636770192265354373513116002688
Line 425, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_app/latest/run.log

  UVM_FATAL @ 1907357488 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (194 [0xc2] vs 190 [0xbe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1907357488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

37.kmac_entropy_refresh.2161397768698254032027974720077275070431334955258320722693075048148492153604
Line 1079, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 19268393768 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (164 [0xa4] vs 142 [0x8e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 19268393768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

41.kmac_stress_all.74139690173499177680906761430030440184454716588978068098296834598537274879556
Line 1993, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest/run.log

  UVM_FATAL @ 53811835150 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (178 [0xb2] vs 44 [0x2c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 53811835150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_stress_all.3723212395796622374719256080163201410835481648697299439894885057856872107871
Line 1345, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest/run.log

  UVM_FATAL @ 94097663567 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (114 [0x72] vs 89 [0x59]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 94097663567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_error has 2 failures.
  - 43.kmac_error.72571889977065731195844674731203502448402606459910099220810207107800363208554
    Line 803, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.kmac_error.49505314842540760507772657412666828708004699811994232244829392461541163217361
    Line 1094, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period.prescaler reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 4.kmac_shadow_reg_errors_with_csr_rw.55418793182610234132859195325439085717081161893148070782309112213952635418352
    Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  87287023 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (73 [0x49] vs 930 [0x3a2]) Regname: kmac_reg_block.entropy_period.prescaler reset value: 0x0
  UVM_INFO @  87287023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.cfg_regwen has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 9.kmac_stress_all.42641383834550116791834765015462796610285762580731645903958531696694015874911
    Line 1526, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 51408360138 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: kmac_reg_block.cfg_regwen
  UVM_INFO @ 51408360138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```