KMAC/UNMASKED Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.261m	16.424ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	36.921us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	55.628us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.190s	1.006ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.140s	1.061ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	301.895us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	55.628us	20	20	100.00
		kmac_csr_aliasing	10.140s	1.061ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	41.760us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	47.059us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.087m	913.684ms	45	50	90.00
V2	burst_write	kmac_burst_write	17.193m	110.447ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	56.693m	100.626ms	50	50	100.00
		kmac_test_vectors_sha3_256	50.999m	91.610ms	50	50	100.00
		kmac_test_vectors_sha3_384	39.274m	249.961ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.533m	199.673ms	50	50	100.00
		kmac_test_vectors_shake_128	1.631h	75.134ms	20	50	40.00
		kmac_test_vectors_shake_256	1.330h	437.792ms	23	50	46.00
		kmac_test_vectors_kmac	5.910s	3.233ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.900s	1.753ms	50	50	100.00
V2	sideload	kmac_sideload	7.428m	19.504ms	50	50	100.00
V2	app	kmac_app	5.870m	50.120ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.500m	29.419ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.839m	33.979ms	48	50	96.00
V2	error	kmac_error	8.477m	100.323ms	49	50	98.00
V2	key_error	kmac_key_error	14.020s	24.037ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.730s	8.540ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.890s	2.676ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.367m	31.087ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	29.500s	3.689ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.385m	100.360ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.860s	54.443us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	66.180us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.590s	64.433us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.590s	64.433us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	36.921us	5	5	100.00
		kmac_csr_rw	1.200s	55.628us	20	20	100.00
		kmac_csr_aliasing	10.140s	1.061ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	576.731us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	36.921us	5	5	100.00
		kmac_csr_rw	1.200s	55.628us	20	20	100.00
		kmac_csr_aliasing	10.140s	1.061ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	576.731us	20	20	100.00
V2		TOTAL			979	1050	93.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.630s	225.625us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.630s	225.625us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.630s	225.625us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.630s	225.625us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.060s	569.015us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	38.550s	2.919ms	5	5	100.00
		kmac_tl_intg_err	5.880s	3.250ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.880s	3.250ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	29.500s	3.689ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.261m	16.424ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.428m	19.504ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.630s	225.625us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	38.550s	2.919ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	38.550s	2.919ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	38.550s	2.919ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.261m	16.424ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	29.500s	3.689ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	38.550s	2.919ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.445m	18.355ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.261m	16.424ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	21.799m	171.828ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1171	1250	93.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.46	95.89	92.38	100.00	69.42	94.11	98.84	96.58

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 62 failures:
- Test kmac_test_vectors_shake_128 has 30 failures.
  - 2.kmac_test_vectors_shake_128.22439131898937181102773513525520762732283225491334687462052052800327961549844
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:86b909bc-4b19-4186-a4c5-27ba0cef956a
```
  - 4.kmac_test_vectors_shake_128.85856089579507488321505967486566808059031155761732746062725542181604744061452
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:6bd51f3a-26e2-4054-8d96-9e556a2ac6de
```
  - ... and 28 more failures.
- Test kmac_test_vectors_shake_256 has 27 failures.
  - 2.kmac_test_vectors_shake_256.84593188357550480053504169333745431945123703262510629658164034560977209730651
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:4f3dcb65-cef2-458d-b0c9-dd3764903e5a
```
  - 5.kmac_test_vectors_shake_256.75385014913775560314070008788094820717070259215465154547200666904554033578715
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:118bc4b8-de77-4375-8ff3-22d0a1ab3c46
```
  - ... and 25 more failures.
- Test kmac_long_msg_and_output has 5 failures.
  - 7.kmac_long_msg_and_output.38859706571142377890971067471195021489042000143071488264098594940733142097559
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:2082ed20-2b7d-4c24-b255-279d45cf584f
```
  - 13.kmac_long_msg_and_output.87038176744226256909211819789168648163532668254260998737821642157589000908582
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:4653bc4b-4abb-4faf-a60c-134802be220f
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 8 failures:

Test kmac_app_with_partial_data has 1 failures.

1.kmac_app_with_partial_data.22592533370802306343406340568610661818148984664792993905304778867812354955418
Line 433, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 1903624689 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (192 [0xc0] vs 85 [0x55]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1903624689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 3 failures.

14.kmac_app.88861894486074605910602417486263463682792197889506413572669180128614262503176
Line 523, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_app/latest/run.log

  UVM_FATAL @ 4037869658 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (204 [0xcc] vs 85 [0x55]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4037869658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.kmac_app.69308692933776026587420327075627685629552590653712395184003045194053811293678
Line 363, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_app/latest/run.log

  UVM_FATAL @ 6680234186 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (17 [0x11] vs 243 [0xf3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6680234186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_entropy_refresh has 2 failures.

17.kmac_entropy_refresh.31594933948006998285339328459686670631597175762705268915090682803826229950925
Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1312340278 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (43 [0x2b] vs 119 [0x77]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1312340278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.kmac_entropy_refresh.30302368481604969829356074697706197854067125669150078591671731699080448628708
Line 717, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 9180641104 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (78 [0x4e] vs 44 [0x2c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9180641104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

38.kmac_stress_all.68974383759434344433937996751745557070059619145576993047382547540329839168410
Line 1081, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest/run.log

  UVM_FATAL @ 4430074464 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (102 [0x66] vs 82 [0x52]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4430074464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.kmac_stress_all.35584579443878916339833473454620065135394609335882859398752862550799299544954
Line 1827, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest/run.log

  UVM_FATAL @ 48339137501 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (103 [0x67] vs 153 [0x99]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 48339137501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.27653198204521258097670883592002939483456636502179113803572919732985077287138
    Line 450, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31396264922 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31396264922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.7000844002988424370997399452672882954306352649024770215652063235175037439179
    Line 549, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11815271231 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11815271231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 4.kmac_stress_all_with_rand_reset.71940282480738645907219512088947581210399578886957857736035597718138136749600
    Line 1936, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 171828403322 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 171828403322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 6.kmac_error.90237049844459702049372149871967482374377376810712853940200137038230216428839
    Line 1079, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```