KMAC/UNMASKED Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.164m	25.570ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	34.215us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.160s	128.011us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.790s	1.947ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.190s	8.615ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.580s	275.455us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.160s	128.011us	20	20	100.00
		kmac_csr_aliasing	9.190s	8.615ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	31.135us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.380s	34.689us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.570m	295.753ms	39	50	78.00
V2	burst_write	kmac_burst_write	19.304m	75.126ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	59.353m	201.537ms	49	50	98.00
		kmac_test_vectors_sha3_256	56.700m	186.247ms	50	50	100.00
		kmac_test_vectors_sha3_384	41.452m	72.701ms	50	50	100.00
		kmac_test_vectors_sha3_512	26.847m	326.165ms	50	50	100.00
		kmac_test_vectors_shake_128	1.654h	51.181ms	18	50	36.00
		kmac_test_vectors_shake_256	1.337h	85.911ms	20	50	40.00
		kmac_test_vectors_kmac	5.950s	1.322ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.780s	963.758us	50	50	100.00
V2	sideload	kmac_sideload	8.096m	20.474ms	50	50	100.00
V2	app	kmac_app	6.494m	96.072ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.201m	37.265ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.348m	29.335ms	49	50	98.00
V2	error	kmac_error	7.199m	57.665ms	50	50	100.00
V2	key_error	kmac_key_error	9.900s	7.605ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.170s	3.269ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.340s	2.431ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	52.490s	6.222ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.036m	1.594ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.698m	76.977ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.810s	22.785us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	54.111us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.330s	194.394us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.330s	194.394us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	34.215us	5	5	100.00
		kmac_csr_rw	1.160s	128.011us	20	20	100.00
		kmac_csr_aliasing	9.190s	8.615ms	5	5	100.00
		kmac_same_csr_outstanding	2.710s	126.368us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	34.215us	5	5	100.00
		kmac_csr_rw	1.160s	128.011us	20	20	100.00
		kmac_csr_aliasing	9.190s	8.615ms	5	5	100.00
		kmac_same_csr_outstanding	2.710s	126.368us	20	20	100.00
V2		TOTAL			972	1050	92.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.410s	48.673us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.410s	48.673us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.410s	48.673us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.410s	48.673us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.210s	420.704us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.056m	4.839ms	5	5	100.00
		kmac_tl_intg_err	5.570s	836.361us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.570s	836.361us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.036m	1.594ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.164m	25.570ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.096m	20.474ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.410s	48.673us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.056m	4.839ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.056m	4.839ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.056m	4.839ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.164m	25.570ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.036m	1.594ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.056m	4.839ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.433m	30.764ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.164m	25.570ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	25.452m	21.486ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1163	1250	93.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.09	95.89	92.27	100.00	66.94	94.11	98.84	96.58

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 74 failures:
- Test kmac_long_msg_and_output has 11 failures.
  - 0.kmac_long_msg_and_output.105377990611142542667663910071824910617176003352978265549968078078184735526290
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:25a796c1-83f8-4a2c-a5ef-c6fcd16997f9
```
  - 2.kmac_long_msg_and_output.79861548632654218571243079653615184085787969696654170744785235221742530277889
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:607fbbe7-741b-4005-b5a3-d8b7a89e5af1
```
  - ... and 9 more failures.
- Test kmac_test_vectors_shake_128 has 32 failures.
  - 0.kmac_test_vectors_shake_128.18242429901797314477691766815071086842799973945794863193612419299430949885858
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:b5ddd142-8756-4c52-b3b4-7c020d3297f7
```
  - 1.kmac_test_vectors_shake_128.53458370298019027846363154870320157986812844352071014937438818992688587880204
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:94315b64-e726-4f03-9e28-5e4c4276c8d5
```
  - ... and 30 more failures.
- Test kmac_test_vectors_shake_256 has 30 failures.
  - 0.kmac_test_vectors_shake_256.59619691408491834048797259449589195341062123741148738055368051365831210207496
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:bbc93beb-a9ce-4ec1-bc3f-75fdb54a44b1
```
  - 1.kmac_test_vectors_shake_256.79768264818470020209999245505420366093581143753295746421229420149582258930994
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:c130cee5-b4f2-4658-bca9-e4b84af8e936
```
  - ... and 28 more failures.
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 3.kmac_test_vectors_sha3_224.91175881564831675086896354034151389634228386282144549197357457267737796952600
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:070a36d0-87ab-4257-982d-269709bf8a5d
```
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.56443333796160955980585615174346724111175724581326611644030145829060002732120
    Line 907, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11687515589 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11687515589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.97577790570092082526306223027588646612217326812556948003979341564315968734831
    Line 2215, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 101467125248 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 101467125248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all has 2 failures.

24.kmac_stress_all.113017712491264934510307859313489430978156192292858663688600104821851408025795
Line 1605, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest/run.log

  UVM_FATAL @ 142280131116 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (3 [0x3] vs 254 [0xfe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 142280131116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.kmac_stress_all.14115389306110324165942411037244918706836444100182080574747671633804612701445
Line 705, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest/run.log

  UVM_FATAL @ 8989473450 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (198 [0xc6] vs 143 [0x8f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8989473450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

42.kmac_entropy_refresh.21873159531611111259556302431264228708538934058878572570836006496109850244614
Line 613, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5448114527 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (16 [0x10] vs 128 [0x80]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5448114527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 1.kmac_stress_all_with_rand_reset.56300564908676928068676261526854932282841639618055525092766281500942392377639
    Line 2118, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 177358070047 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 177358070047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.19694158408721830175037788134505153512164936363749511083951533063612876906989
    Line 354, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25136980509 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 25136980509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 25.kmac_burst_write.64120440364529800910309421231710833823219970526624917051846458870137521062778
    Line 1364, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```