KMAC/UNMASKED Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.229m	11.895ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	44.771us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	102.233us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.080s	5.781ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.600s	2.247ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.490s	521.942us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	102.233us	20	20	100.00
		kmac_csr_aliasing	9.600s	2.247ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	13.432us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	41.071us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.350h	146.516ms	45	50	90.00
V2	burst_write	kmac_burst_write	16.536m	61.247ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.589m	144.417ms	5	5	100.00
		kmac_test_vectors_sha3_256	47.945m	77.235ms	5	5	100.00
		kmac_test_vectors_sha3_384	38.589m	273.758ms	5	5	100.00
		kmac_test_vectors_sha3_512	25.185m	95.989ms	5	5	100.00
		kmac_test_vectors_shake_128	36.935m	92.284ms	5	5	100.00
		kmac_test_vectors_shake_256	47.272m	63.557ms	5	5	100.00
		kmac_test_vectors_kmac	2.490s	130.267us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.490s	98.999us	5	5	100.00
V2	sideload	kmac_sideload	7.985m	23.373ms	50	50	100.00
V2	app	kmac_app	6.353m	77.377ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.938m	13.740ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.490m	20.101ms	49	50	98.00
V2	error	kmac_error	7.675m	20.679ms	50	50	100.00
V2	key_error	kmac_key_error	9.500s	3.369ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.350s	4.529ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.630s	1.467ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.273m	107.691ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	47.710s	4.197ms	50	50	100.00
V2	stress_all	kmac_stress_all	42.215m	272.208ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	14.057us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	320.016us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.350s	54.057us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.350s	54.057us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	44.771us	5	5	100.00
		kmac_csr_rw	1.200s	102.233us	20	20	100.00
		kmac_csr_aliasing	9.600s	2.247ms	5	5	100.00
		kmac_same_csr_outstanding	2.900s	367.182us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	44.771us	5	5	100.00
		kmac_csr_rw	1.200s	102.233us	20	20	100.00
		kmac_csr_aliasing	9.600s	2.247ms	5	5	100.00
		kmac_same_csr_outstanding	2.900s	367.182us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.380s	71.097us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.380s	71.097us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.380s	71.097us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.380s	71.097us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.130s	117.977us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.131m	18.599ms	5	5	100.00
		kmac_tl_intg_err	4.660s	427.408us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.660s	427.408us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	47.710s	4.197ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.229m	11.895ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.985m	23.373ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.380s	71.097us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.131m	18.599ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.131m	18.599ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.131m	18.599ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.229m	11.895ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	47.710s	4.197ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.131m	18.599ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.592m	71.925ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.229m	11.895ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.749m	9.749ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			872	890	97.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.88	95.77	90.51	100.00	67.77	93.67	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.63150607256817151933954483204923504673366703535185320384381449797439721486493
    Line 282, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2744160850 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2744160850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.37410331451229864088607975881597006101035018146928199152740844849129270623833
    Line 362, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7574966709 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7574966709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test kmac_long_msg_and_output has 5 failures.
  - 10.kmac_long_msg_and_output.35936529095252363315795428583475972268047982256380193048168792674758735320071
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:3b8e261e-3621-44f0-b121-f0f5ff1d19ad
```
  - 18.kmac_long_msg_and_output.20549427559886030218376981021468271420325110487257129614034084252227817269635
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:cf2530b9-ca02-4685-9e3d-cd2714c4af8f
```
  - ... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 1.kmac_stress_all_with_rand_reset.29322084017715278954611692178500264420596150396069354008363156539516348251715
    Line 947, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2003395963 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2003395963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.70940438347779435693027231833878257344504002062544102191634855650987544007685
    Line 489, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1579723263 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1579723263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 3 failures:

Test kmac_mubi has 1 failures.

3.kmac_mubi.85701866480220853667826727422796888577121880734030745133145756820330473518801
Line 1117, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_mubi/latest/run.log

  UVM_FATAL @ 71924629534 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (52 [0x34] vs 107 [0x6b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 71924629534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

6.kmac_stress_all.51508726176089792018702185282405005775044871129074779211726935036739702113459
Line 717, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest/run.log

  UVM_FATAL @ 18173777819 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (65 [0x41] vs 205 [0xcd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 18173777819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

11.kmac_entropy_refresh.79618274877855106951525025267686775665418690286043991813894795174838772088352
Line 485, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 14458305126 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (86 [0x56] vs 176 [0xb0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14458305126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---