098010d125| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.041m | 3.927ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.110s | 34.797us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.150s | 114.735us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 18.370s | 5.700ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 9.940s | 1.483ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.500s | 71.282us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.150s | 114.735us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 9.940s | 1.483ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.760s | 32.492us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.400s | 98.334us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 1.427h | 80.478ms | 44 | 50 | 88.00 |
| V2 | burst_write | kmac_burst_write | 16.890m | 246.784ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 46.811m | 123.164ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 49.893m | 85.659ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 36.742m | 837.844ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 13.957m | 18.250ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.182h | 114.191ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 49.633m | 119.235ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 2.530s | 40.828us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.060s | 1.466ms | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.933m | 23.030ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 6.156m | 110.126ms | 49 | 50 | 98.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 7.319m | 83.142ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 6.559m | 202.086ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 8.399m | 21.399ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 11.070s | 6.341ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 43.790s | 6.485ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 39.800s | 12.508ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.142m | 25.368ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 46.960s | 6.077ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 54.733m | 148.744ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 0.870s | 48.135us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.940s | 411.956us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.730s | 538.113us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.730s | 538.113us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.110s | 34.797us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.150s | 114.735us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.940s | 1.483ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.460s | 95.536us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.110s | 34.797us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.150s | 114.735us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.940s | 1.483ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.460s | 95.536us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 683 | 690 | 98.99 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.500s | 61.059us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.500s | 61.059us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.500s | 61.059us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.500s | 61.059us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.190s | 140.630us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.421m | 11.661ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.240s | 255.850us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.240s | 255.850us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 46.960s | 6.077ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.041m | 3.927ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.933m | 23.030ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.500s | 61.059us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.421m | 11.661ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.421m | 11.661ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.421m | 11.661ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.041m | 3.927ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 46.960s | 6.077ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.421m | 11.661ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 6.305m | 13.335ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.041m | 3.927ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 56.040s | 2.510ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 873 | 890 | 98.09 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 23 | 92.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.97 | 95.80 | 90.62 | 100.00 | 68.60 | 93.74 | 99.00 | 96.01 |
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
0.kmac_stress_all_with_rand_reset.7752758957121209383233516680504254609370768216980956094580681076564533084383
Line 319, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5610627793 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5610627793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_stress_all_with_rand_reset.4760116757928372398399419322180070843878545041207386665009650536072060255166
Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 445964459 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 445964459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
23.kmac_long_msg_and_output.2328532277722051768575694129921250900957519046482479442344328203930136461863
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest/run.log
Job ID: smart:217f6a5b-551b-42a7-b08a-088f679afff2
26.kmac_long_msg_and_output.88447490678609182196914793139030236678430455445236477847083163213777338729746
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest/run.log
Job ID: smart:205ce6e6-9614-44a0-baf8-2c7032192492
... and 4 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
7.kmac_stress_all_with_rand_reset.66420572693318793614485199707068838091267749351668401328514365987968324985512
Line 592, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2585201659 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
UVM_INFO @ 2585201659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
34.kmac_app.56960679006380652207481295158282468381748325147645547162419738637613063386846
Line 927, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_app/latest/run.log
UVM_FATAL @ 35784413737 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (181 [0xb5] vs 110 [0x6e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 35784413737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---