KMAC/UNMASKED Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	56.130s	1.015ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	171.408us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	60.847us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.900s	1.512ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.770s	7.396ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.100s	534.542us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	60.847us	20	20	100.00
		kmac_csr_aliasing	11.770s	7.396ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	15.360us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	60.833us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.413h	234.321ms	44	50	88.00
V2	burst_write	kmac_burst_write	20.044m	36.451ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.086h	206.598ms	50	50	100.00
		kmac_test_vectors_sha3_256	1.003h	377.350ms	50	50	100.00
		kmac_test_vectors_sha3_384	43.087m	282.156ms	50	50	100.00
		kmac_test_vectors_sha3_512	28.161m	102.957ms	50	50	100.00
		kmac_test_vectors_shake_128	2.941h	180.135ms	36	50	72.00
		kmac_test_vectors_shake_256	2.985h	3.581s	50	50	100.00
		kmac_test_vectors_kmac	6.100s	538.174us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.650s	986.275us	50	50	100.00
V2	sideload	kmac_sideload	7.982m	63.533ms	50	50	100.00
V2	app	kmac_app	6.511m	65.516ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.887m	56.147ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.032m	42.362ms	49	50	98.00
V2	error	kmac_error	8.769m	80.321ms	49	50	98.00
V2	key_error	kmac_key_error	9.270s	10.462ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.500s	1.338ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.000s	23.624ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.044m	27.157ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	33.660s	1.687ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.114h	243.610ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	12.001us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	35.656us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.440s	139.107us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.440s	139.107us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	171.408us	5	5	100.00
		kmac_csr_rw	1.180s	60.847us	20	20	100.00
		kmac_csr_aliasing	11.770s	7.396ms	5	5	100.00
		kmac_same_csr_outstanding	3.210s	1.920ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	171.408us	5	5	100.00
		kmac_csr_rw	1.180s	60.847us	20	20	100.00
		kmac_csr_aliasing	11.770s	7.396ms	5	5	100.00
		kmac_same_csr_outstanding	3.210s	1.920ms	20	20	100.00
V2		TOTAL			1027	1050	97.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.470s	36.731us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.470s	36.731us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.470s	36.731us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.470s	36.731us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.130s	148.159us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	54.830s	4.757ms	5	5	100.00
		kmac_tl_intg_err	5.640s	2.981ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.640s	2.981ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	33.660s	1.687ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	56.130s	1.015ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.982m	63.533ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.470s	36.731us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.830s	4.757ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.830s	4.757ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.830s	4.757ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	56.130s	1.015ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	33.660s	1.687ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.830s	4.757ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.966m	16.038ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	56.130s	1.015ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	42.902m	75.953ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1219	1250	97.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.35	95.89	92.30	100.00	68.60	94.11	98.84	96.72

Failure Buckets

• Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:

  • Test kmac_long_msg_and_output has 6 failures.

    • 1.kmac_long_msg_and_output.97248685910617611079643166521291835916953204646953983682967039711096414801035
      Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log

        Job ID: smart:e925f181-6a7a-469e-8f10-e389190743d7
      

    • 3.kmac_long_msg_and_output.93481260215705512347449930411698242314566879337874403899321421817537207124556
      Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest/run.log

        Job ID: smart:037f8a94-6c1a-4254-bebf-544502e0dd55
      

    • ... and 4 more failures.

  • Test kmac_test_vectors_shake_128 has 14 failures.

    • 2.kmac_test_vectors_shake_128.81211330624304236738151838524356557106065919338106418706177304785792827851032
      Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log

        Job ID: smart:aec9f98a-18f7-44c3-84f6-32df909deda0
      

    • 3.kmac_test_vectors_shake_128.1429001316436313603906037241286118358465370362919935035100310802881647013976
      Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest/run.log

        Job ID: smart:c24d1db8-4dcc-4250-80d1-5f02316f8177
      

    • ... and 12 more failures.

• UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:

  • Test kmac_stress_all_with_rand_reset has 7 failures.

    • 2.kmac_stress_all_with_rand_reset.49640944309790164555243528810391565821003028671004620932554619085656339999472
      Line 1374, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27435188826 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27435188826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.kmac_stress_all_with_rand_reset.6730795792995115799529061088838649312167277474662656001127867196945145001508
      Line 3351, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 75953011922 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 75953011922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 30.kmac_entropy_refresh.97679368496607758911868312098668750063512798907435617248215940839864668409572
      Line 425, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 28827935384 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (249 [0xf9] vs 9 [0x9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 28827935384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_stress_all has 1 failures.

    • 37.kmac_stress_all.37003081829299613447927228296220108237002670528359158345491217323257066618300
      Line 1591, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest/run.log

        UVM_FATAL @ 18843743858 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (223 [0xdf] vs 159 [0x9f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 18843743858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 8.kmac_stress_all_with_rand_reset.21978536839784716118411392980313961513751411028299764121440851893247312981125
      Line 360, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2294718916 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2294718916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_error has 1 failures.

    • 47.kmac_error.17970603248525397669236403561025753908865343139612034243049667802428363418524
      Line 910, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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