KMAC/UNMASKED Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.067m	2.705ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	35.675us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	179.991us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.390s	8.956ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.350s	731.994us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.580s	144.507us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	179.991us	20	20	100.00
		kmac_csr_aliasing	9.350s	731.994us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	30.685us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.360s	68.115us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.276h	74.968ms	44	50	88.00
V2	burst_write	kmac_burst_write	19.769m	39.852ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.026h	362.652ms	50	50	100.00
		kmac_test_vectors_sha3_256	57.947m	105.395ms	50	50	100.00
		kmac_test_vectors_sha3_384	38.487m	323.051ms	50	50	100.00
		kmac_test_vectors_sha3_512	27.505m	708.951ms	50	50	100.00
		kmac_test_vectors_shake_128	2.997h	174.934ms	22	50	44.00
		kmac_test_vectors_shake_256	2.833h	461.341ms	49	50	98.00
		kmac_test_vectors_kmac	5.880s	263.166us	50	50	100.00
		kmac_test_vectors_kmac_xof	6.070s	264.962us	50	50	100.00
V2	sideload	kmac_sideload	7.268m	220.461ms	50	50	100.00
V2	app	kmac_app	7.106m	76.944ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.175m	51.550ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.668m	7.934ms	47	50	94.00
V2	error	kmac_error	8.686m	77.920ms	50	50	100.00
V2	key_error	kmac_key_error	9.150s	3.380ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	37.650s	5.793ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.550s	1.327ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.087m	7.745ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	36.980s	5.023ms	50	50	100.00
V2	stress_all	kmac_stress_all	52.448m	942.982ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.830s	27.451us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	163.621us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.850s	250.467us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.850s	250.467us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	35.675us	5	5	100.00
		kmac_csr_rw	1.250s	179.991us	20	20	100.00
		kmac_csr_aliasing	9.350s	731.994us	5	5	100.00
		kmac_same_csr_outstanding	2.660s	127.820us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	35.675us	5	5	100.00
		kmac_csr_rw	1.250s	179.991us	20	20	100.00
		kmac_csr_aliasing	9.350s	731.994us	5	5	100.00
		kmac_same_csr_outstanding	2.660s	127.820us	20	20	100.00
V2		TOTAL			1010	1050	96.19
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.520s	392.509us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.520s	392.509us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.520s	392.509us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.520s	392.509us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.840s	239.402us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	53.600s	3.544ms	5	5	100.00
		kmac_tl_intg_err	5.150s	349.530us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.150s	349.530us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	36.980s	5.023ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.067m	2.705ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.268m	220.461ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.520s	392.509us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	53.600s	3.544ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	53.600s	3.544ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	53.600s	3.544ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.067m	2.705ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	36.980s	5.023ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	53.600s	3.544ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.518m	53.878ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.067m	2.705ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	23.578m	259.467ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1202	1250	96.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.47	95.89	92.30	100.00	69.42	94.11	98.84	96.72

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 35 failures:
- Test kmac_test_vectors_shake_128 has 28 failures.
  - 0.kmac_test_vectors_shake_128.39224736083681365953162318193402746966986498563786061603099814864425512390022
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:d5f6b69f-8598-485f-ab40-d877047e9223
```
  - 5.kmac_test_vectors_shake_128.91871963997011951090175566295453351810890896854720722090619364392084649828009
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:6588cee6-7e1f-4c3f-84f8-8d74c43f249f
```
  - ... and 26 more failures.
- Test kmac_long_msg_and_output has 6 failures.
  - 4.kmac_long_msg_and_output.63451536267952527871985873547418388180145153608564972498856384240823825037298
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:7438791f-4de7-446a-88ce-ac3b3db72851
```
  - 7.kmac_long_msg_and_output.34865236121950207596910022571738429042429949570247728946438871972088147436431
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:0b7f492c-4c46-4f84-b45f-69ed5bf365a5
```
  - ... and 4 more failures.
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 15.kmac_test_vectors_shake_256.24473111316038350474997822665230608608144113935598566681670816358739370156255
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:4880bf3b-1ea8-40b3-ae45-8829f9fe9ab4
```
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 1.kmac_stress_all_with_rand_reset.70841826290159701256931793176827352562083862345399272315810719074748630189976
    Line 471, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38705621362 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 38705621362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.20706409168309225175280369714853235342461317887302463824537849896917517332947
    Line 440, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12219793055 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12219793055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_stress_all has 1 failures.

3.kmac_stress_all.74473838518760173877824645821671148030595839204735817048849678044723892643738
Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2149437354 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (160 [0xa0] vs 121 [0x79]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2149437354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

3.kmac_stress_all_with_rand_reset.102337333940035167118486936084076360389558265452687717576001067618312366778413
Line 443, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 9797309937 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (192 [0xc0] vs 120 [0x78]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9797309937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 3 failures.

11.kmac_entropy_refresh.25352272654055215310863627544403223322476540794916159749625525747282894585702
Line 757, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 49265043341 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (253 [0xfd] vs 37 [0x25]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 49265043341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.kmac_entropy_refresh.76001751422345188995644794829011979734869561158567630646191612116014611273357
Line 315, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 7610407819 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (146 [0x92] vs 91 [0x5b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7610407819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 4.kmac_key_error.79512665045265528282780936725587716774705404422996620052470486303104549444109
    Line 267, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 3733475127 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 3733475127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 9.kmac_stress_all_with_rand_reset.100316876840080368739997401318629260307973224981567761764162680468146869138872
    Line 468, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5537941224 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5537941224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```