3707c48f56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.100m | 19.755ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.130s | 66.858us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.200s | 100.214us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 20.790s | 4.979ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 10.580s | 524.541us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.740s | 97.956us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.200s | 100.214us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 10.580s | 524.541us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.730s | 13.511us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.610s | 35.641us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 1.488h | 332.845ms | 46 | 50 | 92.00 |
| V2 | burst_write | kmac_burst_write | 20.300m | 90.775ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 1.032h | 204.657ms | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 59.436m | 402.819ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 44.101m | 1.014s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 25.450m | 302.078ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 2.981h | 173.993ms | 23 | 50 | 46.00 | ||
| kmac_test_vectors_shake_256 | 2.981h | 659.748ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac | 6.770s | 3.526ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 5.690s | 2.866ms | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.182m | 78.638ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 5.898m | 14.750ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 5.494m | 71.771ms | 9 | 10 | 90.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 6.405m | 61.525ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 8.168m | 29.500ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 11.250s | 11.046ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 38.420s | 1.987ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 39.000s | 9.440ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.168m | 20.138ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 33.850s | 1.998ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 38.671m | 23.860ms | 49 | 50 | 98.00 |
| V2 | intr_test | kmac_intr_test | 0.860s | 206.970us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.920s | 28.897us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.070s | 707.131us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.070s | 707.131us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.130s | 66.858us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.200s | 100.214us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.580s | 524.541us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.730s | 389.645us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.130s | 66.858us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.200s | 100.214us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.580s | 524.541us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.730s | 389.645us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1016 | 1050 | 96.76 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.290s | 186.347us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.290s | 186.347us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.290s | 186.347us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.290s | 186.347us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.080s | 143.429us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 55.750s | 4.374ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 4.730s | 747.129us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 4.730s | 747.129us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 33.850s | 1.998ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.100m | 19.755ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.182m | 78.638ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.290s | 186.347us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 55.750s | 4.374ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 55.750s | 4.374ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 55.750s | 4.374ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.100m | 19.755ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 33.850s | 1.998ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 55.750s | 4.374ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.832m | 60.425ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.100m | 19.755ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 45.161m | 105.536ms | 3 | 10 | 30.00 |
| V3 | TOTAL | 3 | 10 | 30.00 | |||
| TOTAL | 1209 | 1250 | 96.72 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 20 | 80.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.29 | 95.89 | 92.30 | 100.00 | 68.60 | 94.11 | 98.84 | 96.29 |
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
Test kmac_test_vectors_shake_128 has 27 failures.
1.kmac_test_vectors_shake_128.23592409599343503225319705239121914021618747071561452158600527811979842907572
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:c7cc1017-d757-4323-b7f2-6af7bf5153de
5.kmac_test_vectors_shake_128.67495885806655053591317225457214907208116849153294455564106826378947110052949
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:9a96773b-fc39-4a07-a428-44cb1ac8cf20
... and 25 more failures.
Test kmac_test_vectors_shake_256 has 1 failures.
9.kmac_test_vectors_shake_256.51449264509543484659785539443652955946083729910921536028615617079343509967374
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_test_vectors_shake_256/latest/run.log
Job ID: smart:b5ce9422-3d21-46e1-a741-34df416dbda9
Test kmac_long_msg_and_output has 4 failures.
13.kmac_long_msg_and_output.12413936805745233083215377452636496776919232325863365179580583526107423566585
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest/run.log
Job ID: smart:bce89579-99e7-4dab-a0c7-945c27a356f0
26.kmac_long_msg_and_output.79460602781313517487490862826465511346740889333520709627980843916350700617747
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest/run.log
Job ID: smart:e2228fcb-8718-4a77-96a1-adc4ee5fedaf
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
1.kmac_stress_all_with_rand_reset.4617537591145919719305688754519016401418818462119692749817001742347248045972
Line 1527, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 134567378169 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 134567378169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_stress_all_with_rand_reset.55142466645473841570038310796815648755242449178705699043091652294121768897759
Line 2167, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 108055016450 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 108055016450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_app_with_partial_data has 1 failures.
0.kmac_app_with_partial_data.110091158416572856178913633528534749555649907123005233682697827457222570810318
Line 397, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log
UVM_FATAL @ 11546679026 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (7 [0x7] vs 170 [0xaa]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 11546679026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
47.kmac_stress_all.70884136254292435522141043372112227772415723809545596941534812093307606434383
Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest/run.log
UVM_FATAL @ 706065309 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (119 [0x77] vs 144 [0x90]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 706065309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---